2017 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) 2017
DOI: 10.23919/sispad.2017.8085328
|View full text |Cite
|
Sign up to set email alerts
|

Simulation based DC and dynamic behaviour characterization of Z2FET

Abstract: This work presents a TCAD investigation of the operation of a Z2FET device for memory application, where the TCAD model is well calibrated to experimental hysteresis curves. The DC operation of the Z2FET has been analyzed for 4 cases, based on the permutations of the front and back gate biases, to identify and compare different modes of operation. The memory mode of operation is under the "Thyristor" like scenario with positive and negative biases applied to the front and back gates respectively. The dynamic p… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1

Citation Types

0
3
0

Year Published

2018
2018
2019
2019

Publication Types

Select...
2
2

Relationship

2
2

Authors

Journals

citations
Cited by 4 publications
(3 citation statements)
references
References 8 publications
0
3
0
Order By: Relevance
“…The Z 2 -FET device [1], [2] is gaining momentum nowadays [3]. This double gated SOI (Silicon-on-Insulator) p-i-n diode is currently being extensively investigated via advanced TCAD simulations [4], [5] and through experiments [6], [7], as a possible DRAM replacement for embedded memory applications. As other single-transistor cells [8], [9], the Z 2 -FET main advantage favoring its adoption is the possibility of getting rid of the external capacitor.…”
Section: Z 2 -Fet Introduction and Basicsmentioning
confidence: 99%
“…The Z 2 -FET device [1], [2] is gaining momentum nowadays [3]. This double gated SOI (Silicon-on-Insulator) p-i-n diode is currently being extensively investigated via advanced TCAD simulations [4], [5] and through experiments [6], [7], as a possible DRAM replacement for embedded memory applications. As other single-transistor cells [8], [9], the Z 2 -FET main advantage favoring its adoption is the possibility of getting rid of the external capacitor.…”
Section: Z 2 -Fet Introduction and Basicsmentioning
confidence: 99%
“…For memory operation, complementary potential barriers are established in the gated and intrinsic regions which prevents/allows electrons and holes to flows through the channel, depending on the electrons amounts stored under the front gate. For detailed memory operation please refer to the previously published papers [15][16][17]. Unless otherwise specified, devices with Lin=Lg=200nm are used for simulation.…”
Section: Device and Tcad Simulation Deckmentioning
confidence: 99%
“…A higher VA (SW1) is required to switch the device on if the initial state is '0' owing to the higher established potential barrier in Gated-SOI region. Consequently, a lower VA is needed to switch the device off [15][16]. The simulations of all specific memory operation such as program '0' (P0), program '1' (P1), hold (H), and read (R) are illustrated in Fig.…”
Section: Device and Tcad Simulation Deckmentioning
confidence: 99%