3D numerical TCAD simulations, based on experimental results, are performed to study the origin of the large Z 2-FET DRAM memory cell-to-cell variability on FD-SOI technology. The body width, cross-section shape and the passivation-induced lateral and top interface state density impacts on the device dynamic memory operation are investigated at room temperature. The width and body shape arise as marginal metrics not strongly inducing fluctuations in the device triggering conditions. However, the interface state (Dit) control, especially at the top of the ungated section, emerges as the main challenge since traps significantly increase the ON voltage variability threatening the capacitor-less DRAM operation.