Simulation methodology for timing analysis and design optimization in digital superconducting electronics

Lo, Sam; Barker, Aaron J.; Whiteley, S.R.; Mlinar, Eric; Chen, Jiajun; Wu, Dehuang; Singhal, K.

doi:10.1109/isqed54688.2022.9806261

Cited by 5 publications

(3 citation statements)

References 9 publications

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“…HSPICE has been enhanced to support SFQ circuit models and improve usability for SCE design. It incorporates features like a Gaussian pulse source, a quantum phase probe, and temperature effects as described in [30]. For RSFQ or ERSFQ logic, the simulation includes support for a configurable current source for appropriate biasing.…”

Section: Design Of Ptl-based Cell Librarymentioning

confidence: 99%

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An Integrated Approach towards VLSI Implementation of SFQ Logic using Standard Cell Library and Commercial Tool Suite

Meher,

Eren Çelik,

Ravi

et al. 2024

J. Phys.: Conf. Ser.

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The semiconductor industry seeks energy-efficient alternatives as Moore’s law nears its limits. The Single Flux Quantum (SFQ) integrated circuits (ICs) using thousands of niobium Josephson junctions (JJs) and operating at 4 K show great promise for digital computing circuits at high speed (>20 GHz) and low power (a few nW per junction). The leading logic families are Rapid Single Flux Quantum (RSFQ), and its energy-efficient variant (ERSFQ). IARPA’s SuperTools program aims to develop integrated design tools for superconductor electronics, targeting SFQ and Adiabatic Quantum-Flux-Parametron (AQFP) logic families. This paper presents a passive transmission line (PTL) based standard cell library for SFQ logic, designed with Synopsys Electronic Design Automation (EDA) software tools for MIT-LL 100μA/μm2 SFQ5ee fab node. The dual RSFQ/ERSFQ standard cell library facilitates seamless integration of SFQ RTL-to-GDS design flow with Synopsys Fusion Compiler, an automated design tool. The SFQ RTL-to-GDS flow entails logic synthesis, checking, placement, clock synthesis, and routing. Row-based placement for library cells and H-tree clock tree structures are employed. Fusion Compiler’s effectiveness is validated with Hypres designs such as finite impulse response (FIR) filters, scalable multiply-accumulate (MAC) units, and memory arrays, comparing single and dual clocking schemes. The synergy between Hypres and Synopsys achieves a milestone by demonstrating the design of a digital superconducting circuit with over 10 million JJs, facilitated by a fully automated design tool for the first time. Challenges in very large-scale SFQ scaling are also discussed.

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Section: Design Of Ptl-based Cell Librarymentioning

confidence: 99%

“…Thus, the optimization is performed for the best-case scenario. Table 1 presents an optimized D flip-flop as an example for global scaling parameter margins, extracted using HSPICE's ".measure tran_cont" commands for logic validation of SFQ circuits [30].…”

Section: Design Of Ptl-based Cell Librarymentioning

confidence: 99%

An Integrated Approach towards VLSI Implementation of SFQ Logic using Standard Cell Library and Commercial Tool Suite

Meher,

Eren Çelik,

Ravi

et al. 2024

J. Phys.: Conf. Ser.

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“…Given that both minutes and seconds operate on a base-60 system and hours on a base-24, there emerges a need for distinct base-60 and base-24 counting modules. This delineation is achieved by modifying the external circuit wiring of the 74LS90 counter chip [2]. Each counter's output signals undergo decoding via a seven-segment display decoder and are subsequently relayed to a six-digit LED seven-segment display, ensuring clear visualization of "hours," "minutes," and "seconds."…”

Section: Introductionmentioning

confidence: 99%

Analysis and design research of digital electronic clocks

Feng

2023

TNS

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A digital electronic clock stands as a pinnacle of modern timing technology, built on digital circuits that offer precise hour, minute, and second tracking and display capabilities. The evolution of integrated circuits, combined with the ubiquitous application of quartz crystal oscillators, has propelled the digital electronic clock into myriad sectors including science, transportation, and finance. These clocks, appreciated for their precision, clarity, stability, and other attributes, vastly differ from their mechanical predecessors. Absent of mechanical transmission devices, they promise longevity and exact timekeeping. Such digitization serves as the foundational technological support for crafting large machinery and precision tools. Delving into the intricacies of digital electronic clocks and broadening their utilization holds substantial real-world relevance. This discourse employs a top-down hierarchical circuit design approach, segmenting the comprehensive circuit into distinct modules. This method not only streamlines its configuration, rendering it user-friendly and legible, but also ensures that each segmented circuit operates as an autonomous entity. This modularity facilitates smoother simulations and circuit modifications, enhancing adaptability and efficiency.

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