Simulation of CMOS IO Standard Based Energy Efficient Gurmukhi Unicode Reader on FPGA

Abstract

In order to fill the research gap of energy efficient hardware design in natural language processing, this project reports the designing of an energy efficient Gurumukhi Unicode Reader on Field Programmable Gate Array (FPGA). To avoid transmission line reflection, a usual problem in hardware design, impedances of transmission line, device and port should be equal. In order to avoid transmission line reflection and make the design energy efficient too, we are using low voltage variants of CMOS: LVCMOS (Low Voltage Complementary Metal oxide Semiconductor) and TTL: LVTTL (Low Voltage TransistorTransistor Logic) I/O standards were used in this project. There is 58.33% and 58.97% decrease in IO power dissipation with LVCMOS12, in compare to LVCMOS25 for 625MHz and 1GHz respectively, with no significant changes in clock power, leakage power and junction temperature. This design is also tested on 25MHz, 125MHz and 25GHz operating frequency with four different LVCMOS.

Power Analysis of Energy Efficient DES Algorithm and Implementation on 28nm FPGA

“…A researcher had done research on energy efficiency of Gurumukhi Unicode reader on FPGA by implementing IO standard [2]. Therefore, we have done analysis on DES algorithm of encryption at different IO standards [2]. one scientist have done research, on digitally controlled impedance IO standard in memory interface design [3]where as we have used IO standard for power analysis which is totally different than this paper [3].…”

“…RELATED WORK Some researcher have implemented IO standard on LVDCI for the analysis of energy efficiency on different temperature i.e., for different regions [1]where we have done totally different analysis on power for different IO standards on DES algorithm [1]. A researcher had done research on energy efficiency of Gurumukhi Unicode reader on FPGA by implementing IO standard [2]. Therefore, we have done analysis on DES algorithm of encryption at different IO standards [2].…”

Effect of Frequency on Energy Efficient Transceiver Design

“…al. [6] energy efficient Gurumukhi Unicode Reader (GUR) is designed by the authors on FPGAs, which is done at a frequency 0f 1GHz by varying IO standards. Md.…”

HSTL IO Standard Based Energy Efficient FIR Filter Design on 28nm FPGA

“…In this paper we have taken HSTL (High Speed Transceiver Logic) IOSTANDARD.HSTL family consists of HSTL _I, HSTL_II, HSTL_I_18 and HSTL_II_18, HSTL_I_12 and the analysis has been done on these IO standards. HSTL I/O standard is used to make this design more energy efficient [13]. There is 32.93% saving in total power dissipation with 1.2 GHz when compared with 2.2GHz as shown in Figure 3 and Table 3.…”