Simulation of nanoscale MOSFETs: a scattering theory interpretation

Ren, Zhibin; Lundstrom, Mark

doi:10.1006/spmi.1999.0798

Cited by 36 publications

(15 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…A simple scattering theory of the MOSFET gives the linear region drain currents as [9] (1a) and the saturated drain current as [7] (1b)…”

Section: Theorymentioning

confidence: 99%

“…New materials are currently being explored to raise the inversion layer mobility (e.g., strained Si [8]), so the question of exactly how the short-channel drain current is related to the long-channel mobility is an important one. In this letter, a scattering theory of the MOSFET [7], [9] is used to develop a simple, quantitative expression that relates the Manuscript linear and saturated drain currents of a nanoscale MOSFET to the near-equilibrium mobility of carriers in a long-channel MOSFET. This new result is consistent with generally observed trends for nanoscale MOSFETs [6], and can be extrapolated to the ballistic limit.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

On the mobility versus drain current relation for a nanoscale MOSFET

Lundstrom

2001

IEEE Electron Device Lett.

220

View full text Add to dashboard Cite

The dependence of the linear and saturated drain current of a nanoscale MOSFET on the near-equilibrium, inversion layer mobility of a long-channel device from the same technology is examined. Simple expressions developed from a scattering theory of the MOSFET provide a quantitative relation between the long-channel mobility and the short-channel drain current. The theory explains the commonly observed mobility-dependence of the linear and saturated drain currents in present-day deep submicron MOSFETs, and the results can be extrapolated all the way to the ballistic limit.

show abstract

“…A simple scattering theory of the MOSFET gives the linear region drain currents as [9] (1a) and the saturated drain current as [7] (1b)…”

Section: Theorymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

On the mobility versus drain current relation for a nanoscale MOSFET

Lundstrom

2001

IEEE Electron Device Lett.

220

View full text Add to dashboard Cite

show abstract

“…Device physics of these MOSFETs were analysed using simple quasi one dimensional models. [9][10][11][12][13] The best modeling approach for design and analysis of nanoscale MOSFETs is presently unclear, though a straightforward application of semiclassical methods that disregards quantum mechanical effects is generally accepted to be inadequate. Quantum mechanical modeling of MOSFETs with channel lengths in the tens of nanometers is important for many reasons:…”

Section: Introductionmentioning

confidence: 99%

Two-dimensional quantum mechanical modeling of nanotransistors

Svizhenko

Anantram

Govindan

et al. 2002

Journal of Applied Physics

432

277

View full text Add to dashboard Cite

“…5 As V GS increases, there occur two competing processes ͑d␣ / dV GS Ͻ 0 due to the increased scattering by the radial electric field and dv inj / dV GS Ͼ 0 again by the radial electric field͒. An almost constant g m suggests that two processes are balancing at high V GS for both V DS = 1 V and 50 mV.…”

mentioning

confidence: 94%

Experimental evidence of ballistic transport in cylindrical gate-all-around twin silicon nanowire metal-oxide-semiconductor field-effect transistors

Cho¹,

Yeo²,

Yeoh³

et al. 2008

Applied Physics Letters

View full text Add to dashboard Cite

We have investigated the electrical characteristics of cylindrical gate-all-around twin silicon nanowire metal-oxide-semiconductor field effect-transistors with 4 nm radius and the gate length ranging from 22 to 408 nm. We observed strong transconductance overshoot in the linear source-drain bias regime in the devices with channel length shorter than 46 nm. The mean free path estimated from the slope of the zero-field one dimensional ballistic resistance measured as a function of device length was almost the same as this length.Silicon-based gate-all-around ͑GAA͒ nanowire transistors are considered promising alternatives to planar metaloxide-semiconductor field-effect transistors ͑MOSFETs͒ because of better gate bias control of electron channels and, thus, reduction of various short channel effects. 1,2 These nanowire devices provide another interesting opportunity since they are expected to have unique one-dimensional electron properties when their radius is small enough and scatterings are suppressed.Ballistic electrons do not go through inelastic scattering while traveling across the channel. Earlier, such perfect ballisticity and conductance quantization at cryogenic temperatures were achieved in patterned one-dimensional GaAs/ AlGaAs heterostructures. 3 Recently, transport in carbon nanotubes has exhibited such ballisticity at room temperature due to its one-dimensional nature with smaller inelastic scattering probability. 4 In conventional planar short channel MOSFETs, some of the carriers can pass the channel when they have large enough velocities. In this case, the ratio of the ballistic electrons over the total number of injected electrons is an important factor. 5 So far, not much experimental information has been obtained on such ballistic transport in recently developed three-dimensional ͑3D͒ MOSFETs even though 3D confinement 6 is expected to modify the electron mobilities ͑thus injection efficiencies͒ and energy relaxation mechanisms.In this letter, we report the electrical characteristics of 4 nm radius cylindrical GAA twin silicon nanowire MOSFETs ͑TSNWFETs͒ with various lengths ͑L's͒ ranging from 22 to 408 nm. We have observed strong overshoots in the low-bias transconductance ͑g m ͒ in the devices with L Ͻ 50 nm. We have analyzed this g m data by means of ballistic transport. The mean free path estimated by zero-field one-dimensional ͑1D͒ resistivity measured from the devices with various lengths is compared with the length scales at which the g m overshoot occurs. Figure 1 shows a schematic and a typical transmission electron microscope ͑TEM͒ image of our TSNWFETs fabricated by full complementary MOS ͑CMOS͒ processes. 1 The formation of the twin nanowires was accomplished by selective epitaxial growth of Si 0.77 Ge 0.23 / Si layers and subsequent removal of the SiGe layer. We performed an in situ steam generated ͑ISSG͒ process to grow gate oxide with a thickness of 3.5 nm. Then, the TiN gate material filling was completed. The TEM image clearly confirmed the circular, crystalline nanowire with ...

show abstract

Simulation of nanoscale MOSFETs: a scattering theory interpretation

Cited by 36 publications

References 14 publications

On the mobility versus drain current relation for a nanoscale MOSFET

On the mobility versus drain current relation for a nanoscale MOSFET

Two-dimensional quantum mechanical modeling of nanotransistors

Experimental evidence of ballistic transport in cylindrical gate-all-around twin silicon nanowire metal-oxide-semiconductor field-effect transistors

Contact Info

Product

Resources

About