On the mobility versus drain current relation for a nanoscale MOSFET

Lundstrom, Mark

doi:10.1109/55.924846

Cited by 220 publications

(101 citation statements)

References 14 publications

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“…7(c)-(d), but it can also change the direction of propagation of one of the two low particles created through the decay of a high energy phonon, thus reducing the current magnitude. This is known as backscattering 45 . While the first effect (additional channels) does not depend on the Si length, the second one (backscattering) increases with L Si , explaining the current characteristics in Fig.…”

Section: B Homogeneous Si Nanowiresmentioning

confidence: 99%

Atomistic modeling of anharmonic phonon-phonon scattering in nanowires

Luisier

2012

Phys. Rev. B

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Phonon transport is simulated in ultra-scaled nanowires in the presence of anharmonic phononphonon scattering. A modified valence-force-field model containing four types of bond deformation is employed to describe the phonon bandstructure. The inclusion of five additional bond deformation potentials allows to account for anharmonic effects. Phonon-phonon interactions are introduced through inelastic scattering self-energies solved in the self-consistent Born approximation in the Nonequilibrium Green's Function formalism. After calibrating the model with experimental data, the thermal current, resistance, and conductivity of <100>-, <110>-, and <111>-oriented Si nanowires with different lengths and temperatures are investigated in the presence of anharmonic phononphonon scattering and compared to their ballistic limit. It is found that all the simulated thermal currents exhibit a peak at temperatures around 200 K if phonon scattering is turned-on while they monotonically increase when this effect is neglected. Finally, phonon transport through Si-Ge-Si nanowires is considered.

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Section: B Homogeneous Si Nanowiresmentioning

confidence: 99%

Atomistic modeling of anharmonic phonon-phonon scattering in nanowires

Luisier

2012

Phys. Rev. B

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“…(b) Gate delay as a function of gate length calculated from transient simulations (labeled 'turn on') and Q/I eff for the InGaAs devices labeled "type 7" in the top panel and for a similarly scaled Si device. Note how, compared to its 'poor' performance estimated from the current drive, InGaAs now outperforms Si, since its lower gate (inversion) capacitance now reduces Q (or, equivalently, the capacitive load) source [31]) force us to revisit some of the assumptions usually made when attempting to understand the basic principles controlling carrier transport in nanometer-scale devices, as exemplified by the 'virtual source' model [32][33][34][35] (also often refereed to as the 'top-of-the-barrier' or the 'backscattering' model, we'll simply call it here the 'virtual source' model).…”

Section: Revisiting the 'Virtual Source Model'mentioning

confidence: 99%

“…(4) Possibly the most significant assumption is the independence of λ on (1) the boundary conditions both upstream and downstream from the virtual source and (2) the possible inhomogeneity in the L-layer (whatever this might be) and, therefore, its relation to the low-field mobility [33]. The implications of these concepts to the future VLSI technology are quite obvious.…”

Section: Assumptions and Issuesmentioning

confidence: 99%

Scaling MOSFETs to 10 nm: Coulomb effects, source starvation, and virtual source model

et al. 2009

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In our attempts to scale FETs to the 10 nm length, alternatives to conventional Si CMOS are sought on the grounds that: (1) Si seems to have reached its technological and performance limits and (2) the use of alternative highmobility channel materials will provide the missing performance. With the help of numerical simulations here we establish the reasons why indeed Si seems to have hit an intrinsic performance barrier and whether or not high mobility semiconductors can indeed grant us our wishes. The role of long-and short-range electron-electron interactions are revisited together with a recent analysis of the historical performance trends. The density-of-states (DOS) bottleneck and source starvation issues are also reviewed to see what advantage alternative substrates may bring us. Finally, the well-known 'virtual source model' is analyzed to assess whether it can be used as a quantitative tool to guide us to the 10 nm gate length.

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“…As the ON-state characteristics of a transistor are also related to their effective mobility [49], [50], the electron mobility reduction due to IRS at low drain bias should be understood in relation with the ON-current reduction at high drain bias. The low-field effective mobility in NWFETs is calculated from the electron density and the conductance using the expression [32], [33] …”

Section: Resultsmentioning

confidence: 99%

Full Three-Dimensional Quantum Transport Simulation of Atomistic Interface Roughness in Silicon Nanowire FETs

Kim

Luisier

Paul

et al. 2011

IEEE Trans. Electron Devices

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Abstract-The influence of interface roughness scattering (IRS) on the performances of silicon nanowire field-effect transistors (NWFETs) is numerically investigated using a full 3D quantum transport simulator based on the atomistic sp 3 d 5 s * tight-binding model. The interface between the silicon and the silicon dioxide layers is generated in a real-space atomistic representation using an experimentally derived autocovariance function (ACVF). The oxide layer is modeled in the virtual crystal approximation (VCA) using fictitious SiO2 atoms. 110 -oriented nanowires with different diameters and randomly generated surface configurations are studied. The experimentally observed ON-current and the threshold voltage is quantitatively captured by the simulation model. The mobility reduction due to IRS is studied through a qualitative comparison of the simulation results with the experimental results.Index Terms-Si gate-all-around nanowire transistors, atomistic, full-band simulations, interface roughness scattering

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On the mobility versus drain current relation for a nanoscale MOSFET

Cited by 220 publications

References 14 publications

Atomistic modeling of anharmonic phonon-phonon scattering in nanowires

Atomistic modeling of anharmonic phonon-phonon scattering in nanowires

Scaling MOSFETs to 10 nm: Coulomb effects, source starvation, and virtual source model

Full Three-Dimensional Quantum Transport Simulation of Atomistic Interface Roughness in Silicon Nanowire FETs

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