Abstract-The influence of interface roughness scattering (IRS) on the performances of silicon nanowire field-effect transistors (NWFETs) is numerically investigated using a full 3D quantum transport simulator based on the atomistic sp 3 d 5 s * tight-binding model. The interface between the silicon and the silicon dioxide layers is generated in a real-space atomistic representation using an experimentally derived autocovariance function (ACVF). The oxide layer is modeled in the virtual crystal approximation (VCA) using fictitious SiO2 atoms. 110 -oriented nanowires with different diameters and randomly generated surface configurations are studied. The experimentally observed ON-current and the threshold voltage is quantitatively captured by the simulation model. The mobility reduction due to IRS is studied through a qualitative comparison of the simulation results with the experimental results.Index Terms-Si gate-all-around nanowire transistors, atomistic, full-band simulations, interface roughness scattering

Abstract-As metal-oxide-semiconductor field-effect transistors (MOSFET) channel lengths (Lg) are scaled to lengths shorter than Lg<8 nm source-drain tunneling starts to become a major performance limiting factor. In this scenario a heavier transport mass can be used to limit source-drain (S-D) tunneling. Taking InAs and Si as examples, it is shown that different heavier transport masses can be engineered using strain and crystal orientation engineering. Full-band extended device atomistic quantum transport simulations are performed for nanowire MOSFETs at Lg<8 nm in both ballistic and incoherent scattering regimes. In conclusion, a heavier transport mass can indeed be advantageous in improving ON state currents in ultra scaled nanowire MOSFETs.

No abstract

No abstract

No abstract