Simulation of self-heating in advanced high-speed sige bipolar circuits using the temperature simulator TeSi

Pfost, Martin; Lachner, Rudolf; Li, Hao

doi:10.1109/smic.2004.1398176

Cited by 13 publications

(7 citation statements)

References 10 publications

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“…Given these temperature rises, the corresponding peak temperatures (

T_{peak - SOA} [^{\circ} normalC]

) as well as the stress levels (

L_{SOA} [%]

) are defined by:

\begin{matrix} true \\ right T_{peak - SOA} & = T_{case} + Δ T_{SOA} \end{matrix}

\begin{matrix} true \\ right L_{SOA} & = \frac{Δ T_{SOA}}{T_{dest} - T_{case}} . \end{matrix}

Since it is assumed that electro‐thermal effects are significant factors for the mean lifetime of the devices, not only analytically approximated, but also simulated temperature rises are investigated. The simulations were performed in an internally used FEM tool . Necessary inputs for the simulation are a time‐dependent curve of the power measurement corresponding to one stress pulse and the geometric design of the DUT.…”

Section: Data and Challengesmentioning

confidence: 99%

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Bayesian Network Model with Application to Smart Power Semiconductor Lifetime Data

2015

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In this article, Bayesian networks are used to model semiconductor lifetime data obtained from a cyclic stress test system. The data of interest are a mixture of log-normal distributions, representing two dominant physical failure mechanisms. Moreover, the data can be censored due to limited test resources. For a better understanding of the complex lifetime behavior, interactions between test settings, geometric designs, material properties, and physical parameters of the semiconductor device are modeled by a Bayesian network. Statistical toolboxes in MATLAB® have been extended and applied to find the best structure of the Bayesian network and to perform parameter learning. Due to censored observations Markov chain Monte Carlo (MCMC) simulations are employed to determine the posterior distributions. For model selection the automatic relevance determination (ARD) algorithm and goodness-of-fit criteria such as marginal likelihoods, Bayes factors, posterior predictive density distributions, and sum of squared errors of prediction (SSEP) are applied and evaluated. The results indicate that the application of Bayesian networks to semiconductor reliability provides useful information about the interactions between the significant covariates and serves as a reliable alternative to currently applied methods.

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“…Given these temperature rises, the corresponding peak temperatures (

T_{peak - SOA} [^{\circ} normalC]

) as well as the stress levels (

L_{SOA} [%]

) are defined by:

\begin{matrix} true \\ right T_{peak - SOA} & = T_{case} + Δ T_{SOA} \end{matrix}

\begin{matrix} true \\ right L_{SOA} & = \frac{Δ T_{SOA}}{T_{dest} - T_{case}} . \end{matrix}

Section: Data and Challengesmentioning

confidence: 99%

“…The simulations were performed in an internally used FEM tool. (12)(13)(14) Necessary inputs for the simulation are a time-dependent curve of the power measurement corresponding to one stress pulse and the geometric design of the DUT. Usually, the output is a temperature map as shown in Fig.…”

Section: Electro-thermal Effectsmentioning

confidence: 99%

Bayesian Network Model with Application to Smart Power Semiconductor Lifetime Data

2015

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“…In this work, the numerical temperature simulator TESI presented in [6] is used to determine the thermal behavior of the device. This computer program solves the heat conduction equation in the time domain, taking the temperaturedependence of the thermal conductivities λ for different materials correctly into account.…”

Section: Numerical Temperature Simulator Tesimentioning

confidence: 99%

Compact nonlinear thermal networks for accurate modeling of smart power ICs

Pfost

Costachescu

2011

ISSCS 2011 - International Symposium on Signals, Circuits and Systems

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Most power semiconductors are subject to substantial self-heating, especially in case of failure conditions such as a shorted load. Therefore, temperature sensors are usually integrated to allow safe turn-off, thus avoiding device destruction, and advanced concepts with multiple sensors, some far away from the heat source, are receiving increased attention. To investigate and optimize the behavior of such designs, system simulations are required that accurately take the thermal coupling between the power device and the temperature sensors into account.For this purpose we present a method for the derivation of nonlinear thermal networks that correctly model the thermal behavior and coupling of on-chip devices. They can easily be included in standard circuit and system simulators and are comparatively simple so that simulation time is not increased significantly. Nevertheless, these networks take all relevant thermal resistances and capacitances of the chip, package, and mounting into account. Moreover, they are accurate even for large temperature swings since they consider the temperaturedependent behavior of silicon. Our approach will be demonstrated for a typical smart power IC and validated by comparison to measurement results.

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“…In this work, an improved version of the 3-D numerical temperature simulator TESI [11] is used for solving the (nonlinear) heat conduction equation in the time domain, correctly modeling the temperature dependence of the thermal conductivity and heat capacitance of silicon. The simulator uses the technique of finite volumes with cuboids as elements, creating the discretization automatically.…”

Section: Electro-thermal Modeling Approachmentioning

confidence: 99%

Measurement and Simulation of Self-Heating in DMOS Transistors up to Very High Temperatures

Pfost

Joos²,

Stecher

2008

2008 20th International Symposium on Power Semiconductor Devices and IC's

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Self-heating can lead to excessive temperatures in large power DMOS transistors, thus restricting their safe operating area (SOA). To explore that limit, the device temperature must be known with sufficient accuracy, which is difficult in advanced BCD technologies. This is because standard measurement methods such as infrared thermography do not show the true device temperature. Also, most (electro-)thermal simulation approaches have not been experimentally verified close to the SOA limits.In this work, a test chip with novel temperature sensors embedded inside the DMOS cell array will be used for accurate measurements of the device temperature. Moreover, a 3-D numerical temperature simulator is extended to correctly consider the temperature-dependent DMOS behavior. Thus, electro-thermal coupling is taken into account while simultaneously calculating the temperatures with high spatial resolution.The validity of the simulator will be demonstrated experimentally by comparison to measurements for temperatures exceeding 500 • C, up to the onset of thermal runaway.

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Simulation of self-heating in advanced high-speed sige bipolar circuits using the temperature simulator TeSi

Cited by 13 publications

References 10 publications

Bayesian Network Model with Application to Smart Power Semiconductor Lifetime Data

Bayesian Network Model with Application to Smart Power Semiconductor Lifetime Data

Compact nonlinear thermal networks for accurate modeling of smart power ICs

Measurement and Simulation of Self-Heating in DMOS Transistors up to Very High Temperatures

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