Simulation Study of the Impact of Quantum Confinement on the Electrostatically Driven Performance of n-type Nanowire Transistors

Abstract

Abstract-In this paper, we have studied the impact of quantum confinement on the performance of n-type silicon nanowire transistors (NWTs) for application in advanced CMOS technologies. The 3-D drift-diffusion simulations based on the density gradient approach that has been calibrated with respect to the solution of the Schrödinger equation in 2-D cross sections along the direction of the transport are presented. The simulated NWTs have cross sections and dimensional characteristics representative of the transistors expected at a 7-nm CMOS technology. Different gate lengths, cross-sectional shapes, spacer thicknesses, and doping steepness were considered. We have studied the impact of the quantum corrections on the gate capacitance, mobile charge in the channel, drain-induced barrier lowering, and subthreshold slope. The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic speed of the NWTs, is also investigated. We have also estimated the optimal gate length for different NWT design conditions.

Impact of quantum confinement on transport and the electrostatic driven performance of silicon nanowire transistors at the scaling limit

“…In our recent publication [27], we reported results for the NWTs with the <110> crystal orientation and similar cross sectional shapes as discussed above but with the 10 times bigger cross sectional area -14 π (44 nm 2 ). In this subsection we expand the already published study by comparing not only the wires with the <110> crystal orientation but also with the <100> channel direction.…”

Correlation between the Golden Ratio and Nanowire Transistor Performance

“…The PS quantum corrections offer a precise charge distribution within the simulated NWTs' channel [5]. And Figure 3 gives the Phi ovals represented on a two-dimensional cross-section at the center of the gate.…”

“…In fact, the literature indicates that the nanowires' cross-sectional shape strongly affects NWTs' gate capacitance and mobile charge [5][6][7]. As a case in point, for an NWT characterized by <110> channel orientation, as well as an extended elliptical cross-section (where the long diameter is parallel to the surface of the silicon wafer), it is associated with the greatest mobile charge for a certain gate voltage.…”

“…The immediate aim of the present research is to examine the distinctive structural and dimensional features of the transistors associated with 5-nm Si CMOS technology, thereby illuminating the quantum mobile charge to gate capacitance ratio [5,7], where the indicator of the intrinsic speed of the NWT is the intrinsic delay (τ) [11]. For the purpose of heightening the degree to which the obtained results are realistic, the simulations take into consideration the effect of quantum confinement, non-equilibrium transport, and contact resistance for such ultra-scaled NWTs.…”

Does a nanowire transistor follow the golden ratio? A 2D Poisson-Schrödinger/3D Monte Carlo simulation study

“…In nanotransistors, the optimal trade-off between performance and leakage currents can be achieved by engineering the device structures. In our previous publications [3], [4], we demonstrated that the crosssectional shape of the nanowires has a strong impact on the gate capacitance and the mobile charge in the NWTs. In particular, the NWT with <110> channel orientation and elongated elliptical cross-section with the long diameter parallel to the silicon wafer surface has the highest mobile charge for a given gate voltage [4].…”