Simulation Study of the Layout Technique for P-hit Single-Event Transient Mitigation via the Source Isolation

et al. 2014

Abstract:The effect of charge sharing on single event upset (SEU) sensitive area of SRAM cells is studied in a 40-nm bulk CMOS technology. All transistors in a 6T SRAM cell are simulated in 3D TCAD models, and SEU sensitive areas are measured in different simulation conditions. We find the charge sharing can reduce SEU sensitive area of SRAM cells. The effect of charge sharing on radiation sensitivity of both PMOS and NMOS are analyzed in depth. The works in this paper can guide the single event rate prediction and the hardened design of SRAMs in advanced technologies.

Section: Simulation Detailsmentioning

confidence: 99%

Effect of charge sharing on SEU sensitive area of 40-nm 6T SRAM cells

et al. 2014

“…Therefore, mitigating the bipolar effect in the PMOS connected the storage node is prior selection for enhanced the SRAM SEU immune. The source isolation technique was presented in [11] and [12], which has been found that it can mitigate P-hit single-event transient perceptibly. Thus, based on the source isolation, the special design of stacking PMOS transistors with layout-level optimized is beneficial for the proposed cell to mitigate the upset from '0' to '1' (occurring on node Q).…”

Section: Proposed Circuitmentioning

confidence: 99%

A radiation harden enhanced Quatro (RHEQ) SRAM cell

Peng

Chen

et al. 2017

This paper intends to present a novel radiation-hardened SRAM cell by using the PMOS transistors stacked (each PMOS is split into two same sizes) and changing the inner topological structure on basis of the Quatro-10T. Combined with layout-level optimization design, the 3-D TCAD mixed-mode simulation results show that the novel design has a great single event upset (SEU) immune. Simultaneously, it is found to be tolerant of partial single-event multiple-node upsets (SEMNUs) due to the charge sharing among off-PMOS transistors. In addition, compared with the Quatro-10T, our proposed structure exhibits larger static noise margin (SNM) as well as lower power consumption in 65 nm COMS technology.

“…Due to the easy look-inside capability, three-dimensional mixed-mode TCAD simulation has been proven to be a useful method to investigate the mechanism of single event charge collection [2,5,9,10,11,12]. In this paper, SET production process is simulated both in a common bulk PMOSFET and in a novel SOI PMOSFET.…”

Section: Device and Simulation Detailsmentioning

confidence: 99%

“…So SET mitigation in PMOSFET becomes a more important issue. In order to reduce the threat of SET in IC in bulk CMOS process, several efficient radiation hardened by design (RHBD) layout techniques are proposed for SET mitigation [5,7,8,9,10,11]. However, none of these RHBD techniques can significantly reduce SET pulse width.…”

Section: Introductionmentioning

confidence: 99%

Research on single-event transient mechanism in a novel SOI CMOS technology

Chen

Chi

et al. 2014

Self Cite

For the first time, compared with common bulk PMOSFETs, single-event transient (SET) mechanism was researched in a novel SOI PMOSFETs using technology computer-aided design mixed-mode numerical (TCAD) simulations. The simulation results showed that, different from the common bulk CMOS technology, diffusion but not bipolar effect is the main mechanism in PMOSFETs fabricated in this novel SOI CMOS technology. The effects of buried oxide (BOX) layer and body tie on SET were also discussed for the PMOSFETs in this technology. The radiation hardened by design (RHBD) layout technique was proposed for further SET mitigation. All of the studies indicated that this novel SOI CMOS technology has the essential advantage for radiation hardened integrated circuit (IC) design.