Simulations of Damage, Crack Initiation, and Propagation in Interlayer Dielectric Structures: Understanding Assembly-Induced Fracture in Dies

Tambat, A.; Lin, Hung-Yun; Subbarayan, Ganesh; Jung, Dae Young; Sammakia, Bahgat

doi:10.1109/tdmr.2012.2195006

Cited by 19 publications

(12 citation statements)

References 28 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…[123][124][125][126][127][128] The low-k ILD and DB material properties most focused on from this viewpoint are Young's modulus and hardness as determined by nanoindentation. 129,130 Due to limitations in spatial resolution and substrate effects that have become increasingly significant as target film thicknesses decrease below 100 nm, 9,131 a number of alternative techniques have recently attracted attention such as contact resonance-atomic force microcopy (CR-AFM) [132][133][134] and bulge testing 135,136 as well as non-contact optical techniques such as picosecond laser ultrasonics (PLU), [137][138][139][140] Brillouin light scattering (BLS), [141][142][143][144][145][146] and surface acoustic wave spectroscopy (SAWS) 146,147 .…”

Section: -122mentioning

confidence: 99%

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

King

2014

ECS J. Solid State Sci. Technol.

133

115

View full text Add to dashboard Cite

Over the past decade, the primary focus for improving the performance of nano-electronic metal interconnect structures has been to reduce the impact of resistance-capacitance (RC) delays via utilizing insulating dielectrics with ever lower values of dielectric permittivity. The integration and implementation of such low dielectric constant (i.e. low-k) materials has been fraught with numerous challenges. For intermetal and interlayer (ILD) low-k dielectrics, these challenges have been largely associated to integration with metal interconnect fabrication processes and well documented and reviewed in the literature. Although equally important, less attention has been given to other low-k dielectrics utilized in metal interconnect structures that are commonly referred to as low-k dielectric barriers (DB), etch stops (ES), and/or Cu capping layers (CCL). These materials present numerous challenges as well for integration into metal interconnect fabrication processes. However, they also have more stringent integrated functionality requirements relative to low-k ILD materials that serve only a basic purpose of electrically isolating adjacent metal lines. In this article, we review the integration challenges and associated integrated functionality requirements for low-k DB/ES/CCL materials with a focus on the current status and future direction needed for these materials to facilitate both Moore's law (i.e. More Moore) and More than Moore scaling.

show abstract

Section: -122mentioning

confidence: 99%

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

King

2014

ECS J. Solid State Sci. Technol.

133

115

View full text Add to dashboard Cite

show abstract

“…This leads to large leakage currents and can contribute to a range of other electrical reliability issues [ 25 , 26 , 27 ]. BEOL process-induced chemical modification of p-SiOCH also contributes to many undesirable physical property deviations that are most prominently manifested via a range of thermal–mechanical reliability failures [ 28 , 29 , 30 ]. A previous study conducted by Zin et al clearly showed that exposing p-SiCOH to oxidizing plasmas results in a loss of hydrophobicity, as well as thermo–mechanical stability due to the replacement of terminal CH 3 groups with silanol (OH) groups [ 31 ].…”

Section: Introductionmentioning

confidence: 99%

Enhanced Thermo–Mechanical Reliability of Ultralow-K Dielectrics with Self-Organized Molecular Pores

Ma¹,

Bang

Son

et al. 2021

Materials

View full text Add to dashboard Cite

This paper reported the enhancement in thermo-mechanical properties and chemical stability of porous SiCOH dielectric thin films fabricated with molecularly scaled pores of uniform size and distribution. The resulting porous dielectric thin films were found to exhibit far stronger resistance to thermo-mechanical instability mechanisms common to conventional SiCOH dielectric thin films without forgoing an ultralow dielectric constant (i.e., ultralow-k). Specifically, the elastic modulus measured by nano-indentation was 13 GPa, which was substantially higher than the value of 6 GPa for a porous low-k film deposited by a conventional method, while dielectric constant exhibited an identical value of 2.1. They also showed excellent resistance against viscoplastic deformation, as measured by the ball indentation method, which represented the degree of chemical degradation of the internal bonds. Indentation depth was measured at 5 nm after a 4-h indentation test at 400 °C, which indicated an ~89% decrease compared with conventional SiCOH film. Evolution of film shrinkage and dielectric constant after annealing and plasma exposure were reduced in the low-k film with a self-organized molecular film. Analysis of the film structure via Fourier-transform infrared (FTIR) spectroscopy and X-ray photoelectron spectroscopy (XPS) indicated an increase in symmetric linear Si–O–Si molecular chains with terminal –CH3 bonds that were believed to be responsible for both the decrease in dipole moment/dielectric constant and the formation of molecular scaled pores. The observed enhanced mechanical and chemical properties were also attributed to this unique nano-porous structure.

show abstract

“…Another approach to reduce meshing effort and thus simulation time is to substitute regions that require a very dense mesh (for instance the many metal fingers of the LDMOS with the vias and contacts) by an equivalent layer consisting of a single homogeneous material, e.g., as described in [6]- [9]. This results in much easier meshing, however, simulation accuracy is lower because the structure of the substituted regions is lost.…”

Section: Introductionmentioning

confidence: 99%

Efficient Simulation of Thermo-Mechanical Stress in the On-Chip Metallization of Integrated Power Semiconductors

Pham

Ritter

Pfost

2017

IEEE Trans. Device Mater. Relib.

View full text Add to dashboard Cite

Integrated power semiconductors are often used for applications with cyclic on-chip power dissipation. This leads to repetitive self-heating and thermo-mechanical stress, causing fatigue on the on-chip metallization and possibly destruction by short circuits. Because of this, an accurate simulation of the thermo-mechanical stress is needed already during the design phase to ensure that lifetime requirements are met. However, a detailed thermo-mechanical simulation of the device, including the on-chip metallization is prohibitively time-consuming due to its complex structure, typically consisting of many thin metal lines with thousands of vias. This paper introduces a two-step approach as a solution for this problem. First, a simplified but fast simulation is performed to identify the device parts with the highest stress. After, precise simulations are carried out only for them. The applicability of this method is verified experimentally for LDMOS transistors with different metal configurations. The measured lifetimes and failure locations correlate well with the simulations. Moreover, a strong influence of the layout of the on-chip metallization lifetime was observed. This could also be explained with the simulation method. Index Terms-Integrated power technologies, integrated circuit modeling, power semiconductor devices, on-chip metallization, thermo-mechanical stress, degradation, reliability.

show abstract

Simulations of Damage, Crack Initiation, and Propagation in Interlayer Dielectric Structures: Understanding Assembly-Induced Fracture in Dies

Cited by 19 publications

References 28 publications

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

Enhanced Thermo–Mechanical Reliability of Ultralow-K Dielectrics with Self-Organized Molecular Pores

Efficient Simulation of Thermo-Mechanical Stress in the On-Chip Metallization of Integrated Power Semiconductors

Contact Info

Product

Resources

About