Simulative characterization of the stability for second order voltage switched CP-PLL

Ali, Ehsan; Rahajandraibe, Wenceslas; Haddad, Fayrouz; Hedayat, Christian; Hangmann, Christian

doi:10.1109/mwscas.2013.6674608

Cited by 3 publications

(3 citation statements)

References 6 publications

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“…We begin by computing the Jacobian (9) of the vector field (5). We linearize the system at the locked state, i.e., θ e = 0, because in that case the Jacobian does not depend on the state of (5) and we do not need to compute the associated equilibrium state.…”

Section: Stability Analysismentioning

confidence: 99%

“…We linearize the system at the locked state, i.e., θ e = 0, because in that case the Jacobian does not depend on the state of (5) and we do not need to compute the associated equilibrium state. The subsequent linear model is a good approximation of (5) if |θ e | is sufficiently small. For f (x(t), θ 1 (t)) := Ax(t) + B sin (θ 1 (t) + Cx(t)) we obtain…”

Section: Stability Analysismentioning

confidence: 99%

“…However, in the presence of noise, this tracking is degraded and the signals may not lock exactly. In practice, designers account for the presence of noise by placing the system poles further into the left-half plane and by making conservative design decisions [4,5].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Phase-locked loop stability based on stochastic bounds

Baker

Leung

Nielsen

2015

Analog Integr Circ Sig Process

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In this paper we study the stability of a phase-locked loop (PLL) in the presence of noise. We represent the noise as Brownian motion and model the circuit as a nonlinear stochastic differential equation, with the noise lumped at the phase detector input. We show that for the PLL, the theory of asymptotics of singular diffusions can be applied and we use this theory to develop a new figure of merit which we call a stability margin. The stability margin provides easily computable bounds on the acceptable noise levels for which stability is guaranteed. Through simulation, we show that such a sufficient bound provides a realistic prediction for PLL stability.

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Section: Stability Analysismentioning

confidence: 99%

Section: Stability Analysismentioning

confidence: 99%

See 1 more Smart Citation

Phase-locked loop stability based on stochastic bounds

Baker

Leung

Nielsen

2015

Analog Integr Circ Sig Process

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Simulation and validation of arbitrary ordered VSCP-PLLs using event-driven macromodeling

Ali¹,

Rahajandraibe²,

Haddad³

et al. 2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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In modern electronic systems, PLLs are widely used for frequency synthesis applications. PLLs have a mixed analog-digital nature, which makes difficult to characterize its overall non-linear behavior using general theory of feedback system. To simulate the transient behavior of the PLL often the circuit level simulator is used. The frequency divider circuit separates the loop in low and high frequency parts leading to a small sampling time and a high simulation time, which are major technological bottlenecks using behavioral or transistor level models. In this paper, electrical simulations of an arbitrary ordered PLL operating with a voltage switched charge pump (VSCP) are performed. By simulating each block of the VSCP-PLL within the loop using transistor level model, the results were used to setup macroscopic parameters within the Event-Driven model. The Event-Driven simulation efficiently characterizes the off-locking transient domain in a very short time. The Event-Driven simulations are validated by transistor level simulations of arbitrary ordered integer-N VSCP-PLL designed in Cadence (Virtuoso) using CMOS technologies (130nm and 65nm)

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Analyzing the Impact of Loop Parameter Variations on the Transient Response of Second Order Voltage-Switched CP-PLL

Ali

Narwani

Bughio

et al. 2021

Eng. Technol. Appl. Sci. Res.

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The analysis of the behavior of Charge Pump Phase-Locked Loop (CP-PLL) is a challenging task due to its mixed-signal architecture. Out of its two types, i.e. Current Switched CP-PLL (CSCP-PLL) and Voltage Switched CP-PLL (VSCP-PLL), the prior produces symmetrical pump currents, resulting in an appropriate transient performance to be analyzed. The loop parameters are important to set the gain, target frequency, and assure the stability of the system. The more important is the bandwidth of the loop, which is dependent on the loop filter parameters to perform stable operation and locking time. In this paper, the impact of loop parameter variations on the overall transient behavior of the system is investigated. It has been shown that loop parameters play an important role to ease the design of mixed-signal PLLs.

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Simulative characterization of the stability for second order voltage switched CP-PLL

Cited by 3 publications

References 6 publications

Phase-locked loop stability based on stochastic bounds

Phase-locked loop stability based on stochastic bounds

Simulation and validation of arbitrary ordered VSCP-PLLs using event-driven macromodeling

Analyzing the Impact of Loop Parameter Variations on the Transient Response of Second Order Voltage-Switched CP-PLL

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