Simulator generation using an automaton based pipeline model for timing analysis

Kassem, Rola; Briday, Mikaël; Béchennec, Jean-Luc; Trinquet, Yvon; Savaton, Guillaume

doi:10.1109/imcsit.2008.4747313

Cited by 6 publications

(6 citation statements)

References 13 publications

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“…x γ a→b (14) This process can be iterated for each part entirely bounded by the event e resulting in:…”

Section: Bounding the Part Countersmentioning

confidence: 99%

See 1 more Smart Citation

A Framework for Calculating WCET Based on Execution Decision Diagrams

Bai¹,

Cassé²,

Michiel³

et al. 2022

ACM Trans. Embed. Comput. Syst.

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Due to the dynamic behaviour of acceleration mechanisms such as caches and branch predictors, static Worst-Case Execution Time ( wcet ) analysis methods tend to scale poorly to modern hardware architectures. As a result, a trade-off must be found between the duration and the precision of the analysis, leading to an overestimation of the wcet bounds. In turn, this reduces the schedulability and resource usage of the system. In this paper we present a new data structure to speed up the analysis: the eXecution Decision Diagram ( xdd ), which is an ad-hoc extension of Binary Decision Diagrams tailored for wcet analysis problems. We show how xdd s can be used to represent efficiently execution states in a modern hardware platform. Moreover, we propose a new process to build the Integer Linear Programming system of the Implicit Path Enumeration Technique using xdd . We use benchmark applications to demonstrate how the use of an xdd substantially increases the scalability of wcet analysis and the precision of the obtained wcet .

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“…x γ a→b (14) This process can be iterated for each part entirely bounded by the event e resulting in:…”

Section: Bounding the Part Countersmentioning

confidence: 99%

“…A irst kind of generic method to compute basic block execution times was proposed by Kassem et al [14]. It uses automata to represent the diferent states of the pipeline.…”

Section: Related Workmentioning

confidence: 99%

A Framework for Calculating WCET Based on Execution Decision Diagrams

Bai¹,

Cassé²,

Michiel³

et al. 2022

ACM Trans. Embed. Comput. Syst.

View full text Add to dashboard Cite

show abstract

“…A rst kind of generic method to compute basic block execution times was proposed by Kassem et al in [12]. It uses automata to represent the dierent states of the pipeline.…”

Section: Related Workmentioning

confidence: 99%

Improving the Performance of WCET Analysis in the Presence of Variable Latencies

Bai

Cassé

Michiel

et al. 2020

The 21st ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems

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Due to the dynamic behaviour of acceleration mechanisms such as caches and branch predictors, static Worst-Case Execution Time () analysis methods tend to scale poorly to modern hardware architectures. As a result, a tradeo must be made between the duration and the precision of the analysis, leading to an overestimation of the bounds. This in turn reduces the schedulability and resource usage of the system. In this paper we present a new data structure to speed up the analysis: the eXecution Decision Diagram (), which is an ad-hoc extension of Binary Decision Diagrams tailored for analysis problems. We show how s can be used to represent eciently execution states and durations of instruction sequencesn a modern hardware platform. We demonstrate on realistic applications how the use of an substantially increases the scalability of analysis.

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“…The execution model of this simulator is a finite state automaton generated from the description of the pipeline in HARMLESS. More details may be found in [5] A state of the automaton represents the pipeline state at a particular time. At each clock cycle, the pipeline goes from one state to another according to hazards.…”

Section: Micro-architecture Viewmentioning

confidence: 99%

“…The work presented in this paper is a part of a larger project aiming at the realization of a simulator offering ISS and CAS possibilities, and used for the design of real-time embedded systems. Some information about the CAS part are quickly given in this paper and the interested reader can refer to [5] for more details. This paper focuses on the automatic generation of an ISS.…”

Section: Introductionmentioning

confidence: 99%

Instruction Set Simulator Generation Using HARMLESS, a New Hardware Architecture Description Language

Kassem¹,

Briday²,

Béchennec³

et al. 2009

Proceedings of the Second International ICST Conference on Simulation Tools and Techniques

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Instruction set simulators are commonly used in embedded system development processes for early functional validation of code and exploration of new instruction set design. Such a simulator can be either hand-written or generated automatically, based on a Hardware Architecture Description Language. Automatically generated simulators are more maintainable and are faster to develop, but they also generally suffer from low performances in simulation speed and a lack of expressivity in the description. This paper introduces HARMLESS, a new language to automatically generate instruction set simulators. It differs from other languages in many ways: it resolves most expressivity issues and naturally offers a flexible description by explicitly splitting the syntax (mnemonic), format (binary code) and behavior descriptions. Thus, it allows an incremental description, starting for example by the disassembler (requiring format and syntax descriptions). When the first two descriptions are validated, the behavior description is added to obtain the simulator. Some results are also presented on the simulator build process, especially on the decoder generation. An instruction cache is also introduced to speed up simulation in the same order of magnitude as hand-written simulators. Some experimental results are eventually presented.

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Simulator generation using an automaton based pipeline model for timing analysis

Cited by 6 publications

References 13 publications

A Framework for Calculating WCET Based on Execution Decision Diagrams

A Framework for Calculating WCET Based on Execution Decision Diagrams

Improving the Performance of WCET Analysis in the Presence of Variable Latencies

Instruction Set Simulator Generation Using HARMLESS, a New Hardware Architecture Description Language

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