Simultaneous analog placement and routing with current flow and current density considerations

Abstract

Current-flow and current-density are two major considerations for placement and routing of analog layout synthesis. The current-flow constraints are specified to the critical nets with monotonic current/signal paths to reduce parasitic impacts. The current-density constraints are usually specified on the nets with variable wire widths to avoid the IR-drop and electromigration problems. In this paper, we propose the first work to simultaneously consider current-flow and current-density constraints while placing and routing the analog circuits with minimized chip area, routed wirelength, bend numbers, via counts, and coupling noise at the same time. We first present an enhanced B*-tree representation to simultaneously model modules and interconnects for an analog circuit. Then a simultaneous placement and routing algorithm is presented to generate a layout while satisfying the current-flow and current-density constraints with minimized chip area, routed wirelength, bend numbers, via counts, and coupling noise. Experimental results show that our approach can obtain better layout results and satisfy all specified constraints while optimizing circuit performance.

Layout-dependent-effects-aware analytical analog placement

“…Because no existing work simultaneously considers the WPE, LOD, and OSE of LDEs in analog placement, we compared our work with the stochastic-based analog placement algorithms [14] and [19]. We extended both [14] and [19] with the consideration of LDEs by adding an LDE cost from the three exact LDE models and a perturbation to change the finger number of devices.…”

“…We extended both [14] and [19] with the consideration of LDEs by adding an LDE cost from the three exact LDE models and a perturbation to change the finger number of devices. Since the work [19] did not consider routing issues in the placement stage, all the results generated by [19] are hard to be routed and fail on the simulations.…”

“…Since the work [19] did not consider routing issues in the placement stage, all the results generated by [19] are hard to be routed and fail on the simulations. Therefore, we only compared our work with [14] which simultaneously considers placement and routing. Columns 17 to 18 in Table 2 and Columns 14 to 15 in Table 3 compare the placement runtime between [14] and our approach for the two analog circuits.…”

“…Therefore, we only compared our work with [14] which simultaneously considers placement and routing. Columns 17 to 18 in Table 2 and Columns 14 to 15 in Table 3 compare the placement runtime between [14] and our approach for the two analog circuits. The experimental results show that our analytical analog placement flow runs much faster than [14] for both circuits, because the work [14] requires to calculate the distance between adjacent modules/wells for the LDE cost, especially the cost for OSE, during each packing.…”

“…Although the placement problems have been widely studied for digital circuits, analog circuit placement requires to consider various complex constraints, and thus the techniques for digital circuits might not apply to analog circuits well. To handle the analog placement problem, most previous works apply the topological floorplan representations with the simulated annealing (SA) scheme to seek for desired placements [10,14,19]. Nevertheless, stochasticbased analog placement algorithms might require more running time and are thus hard to achieve desired placement results when considering multiple objectives of the LDEs in large-scale analog circuits.…”