Simultaneous Depth and Area Minimization in LUT-based FPGA Mapping

Cong, Jason; Hwang, Yean-Yow

doi:10.1109/fpga.1995.241947

Cited by 50 publications

(46 citation statements)

References 7 publications

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“…is the criticality for each connection and is a tradeoff factor between timing and wire congestion for a resource node. is defined as (18) where is the slack of each connection and is the critical path delay, both analyzed by STA. MaxCrit is the maximum criticality that any connection can have, and is the criticality component.…”

Section: A Timing-driven Routing Pathfindermentioning

confidence: 99%

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Stochastic Physical Synthesis Considering Prerouting Interconnect Uncertainty and Process Variation for FPGAs

Lin

Hutton

2008

IEEE Trans. VLSI Syst.

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Process variation and prerouting interconnect delay uncertainty affect timing and power for modern VLSI designs in nanometer technologies. This paper presents the first in-depth study on stochastic physical synthesis algorithms leveraging statistical static timing analysis (SSTA) with process variation and prerouting interconnect delay uncertainty for field-programmable gate arrays (FPGAs). Evaluated by SSTA using the placed and routed circuits, the stochastic clustering, placement, and routing reduce the mean delay by 5.0%, 4.0%, and 1.4%, respectively, and reduce the standard deviation of delay by 6.4%, 6.1%, and 1.4%, respectively for MCNC designs. The majority of improvements come from modeling interconnect delay uncertainty for clustering and from considering process variation for placement, while routing has less improvement on delay. In addition, we study the interaction between each individual design stage. When applying all stochastic algorithms concurrently, the mean delay and standard deviation are reduced by 6.2% and 7.5%, respectively. On the other hand, stochastic clustering with deterministic placement and routing is a good flow with little change to the entire flow, but the mean delay is reduced by 5.0%, the standard deviation is reduced by 6.4%, and the runtime is slightly reduced compared to the deterministic flow. Finally, while its improvement over timing is small, stochastic routing is able to reduce the total wire length by 4.5% and to reduce the overall runtime by 4.2% compared to deterministic routing.

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Section: A Timing-driven Routing Pathfindermentioning

confidence: 99%

“…The baseline FPGA synthesis flow (see Fig. 1) consists of SIS [17], CutMap [18], T-VPack [19], and VPR [19], which are the commonly used algorithms in academic research. The same synthesis result is applied to all chips for the same application.…”

Section: Introductionmentioning

confidence: 99%

Stochastic Physical Synthesis Considering Prerouting Interconnect Uncertainty and Process Variation for FPGAs

Lin

Hutton

2008

IEEE Trans. VLSI Syst.

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“…The complexity of the LURU algorithm is therefore O(K(m+n)), in which n is the number of gates in the circuit, m is the number of wires, and K is the input cardinality of the LUTs used to implement the circuit. The complexity of FlowMap is O(Kmn), and the complexity of CutMap is O(2Kmn[K/2]+1) [9], [10]. LURU has reasonable complexity with respect to both FlowMap and CutMap.…”

Section: Algorithm Complexitymentioning

confidence: 98%

“…LURU takes advantage of the parallelism of CAM to globally search an entire circuit. This approach produces improved area results over the technology mapping algorithms FlowMap and CutMap [9], [10]. Section 2 of this paper describes LURU's data representation and algorithm flow.…”

Section: Introductionmentioning

confidence: 98%

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LURU: global-scope fpga technology mapping with content-addressable memories

Lucas

Hoare

Kourtev

et al.

Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004.

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This paper proposes a technique for area-optimized FPGA technology mapping. The LURU algorithm maps a combinational circuit to a network of K-input lookup tables (LUTs). The LURU algorithm uses content addressable memory (CAM) to enable parallel pattern matching in a Boolean network. As a result, it is possible to quickly perform global searches within an entire Boolean network, thus increasing the quality of results compared to algorithms of local scope. To utilize CAM for the LURU algorithm, a circuit is described as a set of one dimensional text strings, each of which independently represents the topology of a portion of the circuit.The LURU algorithm was tested with specially partitioned circuits from the ISCAS '85 set of combinational benchmarks. These results are compared with results obtained from the mapping algorithms FlowMap and CutMap. It is demonstrated that using LURU leads to an average of 25% area improvement over both FlowMap and CutMap.

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Power Dissipation Impact of the Technology Mapping Synthesis on Look-Up Table Architectures

Veredas

Carrabina

2005

Lecture Notes in Computer Science

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Simultaneous Depth and Area Minimization in LUT-based FPGA Mapping

Cited by 50 publications

References 7 publications

Stochastic Physical Synthesis Considering Prerouting Interconnect Uncertainty and Process Variation for FPGAs

Stochastic Physical Synthesis Considering Prerouting Interconnect Uncertainty and Process Variation for FPGAs

LURU: global-scope fpga technology mapping with content-addressable memories

Power Dissipation Impact of the Technology Mapping Synthesis on Look-Up Table Architectures

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