Stochastic Physical Synthesis Considering Prerouting Interconnect Uncertainty and Process Variation for FPGAs

Abstract

Process variation and prerouting interconnect delay uncertainty affect timing and power for modern VLSI designs in nanometer technologies. This paper presents the first in-depth study on stochastic physical synthesis algorithms leveraging statistical static timing analysis (SSTA) with process variation and prerouting interconnect delay uncertainty for field-programmable gate arrays (FPGAs). Evaluated by SSTA using the placed and routed circuits, the stochastic clustering, placement, and routing reduce the mean delay by 5.0%, 4.0%, and 1.4%, respectively, and reduce the standard deviation of delay by 6.4%, 6.1%, and 1.4%, respectively for MCNC designs. The majority of improvements come from modeling interconnect delay uncertainty for clustering and from considering process variation for placement, while routing has less improvement on delay. In addition, we study the interaction between each individual design stage. When applying all stochastic algorithms concurrently, the mean delay and standard deviation are reduced by 6.2% and 7.5%, respectively. On the other hand, stochastic clustering with deterministic placement and routing is a good flow with little change to the entire flow, but the mean delay is reduced by 5.0%, the standard deviation is reduced by 6.4%, and the runtime is slightly reduced compared to the deterministic flow. Finally, while its improvement over timing is small, stochastic routing is able to reduce the total wire length by 4.5% and to reduce the overall runtime by 4.2% compared to deterministic routing.

Classification on variation maps: a new placement strategy to alleviate process variation on FPGA

“…In addition, SSTA enables a trade-off between product parametric yield and speed. The results of SSTA-driven optimisation reported so far are promising [1].…”

Statistical Generic and Chip-Specific Skew Assignment for Improving Timing Yield of FPGAs

“…For instance, if a chip has a critical path delay that exceeds the specification by 1.4%, it is placed in the [1,2) delay bin meaning that the clock period of the chip exceeds timing specification by 1-2%. From the figure we can see that most of the failing chips fall in the bins (0,1] and (1,2]. Furthermore, about 88% of failed chips fall in the extended delay bin (0,5].…”

“…To alleviate the problems due to variability, statistical optimization techniques have been adopted for a long time by ASIC designers. Recently the FPGA community has also started to take note of the potential pitfalls associated with not considering process variations in the design phase( [1], [2], [3]). Statistical static timing analysis has been widely used to account for variations and to produce tighter delay distributions to improve timing yield.…”

Mitigation of process variation effect in FPGAs with partial rerouting method

“…Instead of static and deterministic timing of switches and interconnects, the delay of each element in the routing graph is defined as a distribution which is used during the SSTA routing process to evaluate the cost and path delay [3]. The distribution of process variation is modelled based on either historical data or collected variation maps.…”