Simultaneous EUV flare- and CMP-aware placement

Liu, Chi-Yuan; Chang, Yao-Wen

doi:10.1109/iccd.2014.6974689

Cited by 6 publications

(2 citation statements)

References 20 publications

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“…To consider metal density distribution at the design stage, Liu and Chang [21] proposed the first work of simultaneous EUV flare-and CMP-aware placement. An expected metal density map is first constructed by considering flare mitigation and density uniformity.…”

Section: Flare Effectmentioning

confidence: 99%

EUV and e-beam manufacturability

Chang

Liu

Fang

2015

Proceedings of the 52nd Annual Design Automation Conference

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As process nodes continue to shrink, the semiconductor industry faces severe manufacturing challenges. Two most expected technologies may push the limits of next-generation lithography: extreme ultraviolet lithography (EUVL) and electron beam lithography (EBL). EUVL works by emitting intense beams of ultraviolet light that are reflected from a reflective mask into a resist for nanofabrication, while EBL scans focused beams of electrons to directly draw high-resolution feature patterns on a resist without employing any mask. Each of the two technologies encounters unique design challenges and requires solutions for a breakthrough. In this paper, we focus on the design-for-manufacturability issues for EUVL and EBL. We investigate the most critical design challenges of the two technologies, flare and shadowing effects for EUVL, and heating, stitching, fogging, and proximity effects for EBL. Preliminary solutions for these effects are explored, which can contribute to the continuing scaling of the CMOS technology. Finally, we provide future research directions for these key effects.Extreme ultraviolet lithography, electron beam lithography, physical design, design for manufacturability, flare effect, shadowing effect, heating effect, stitching effect, proximity effect, fogging effect *

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Section: Flare Effectmentioning

confidence: 99%

EUV and e-beam manufacturability

Chang

Liu

Fang

2015

Proceedings of the 52nd Annual Design Automation Conference

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“…Besides general lithography and MPL aware placement, there are some other researches focusing on emerging technology, like electron beam lithography (EBL), extreme ultra violet (EUV), and Directed Self-Assembly (DSA) [32][33][34][35]. For example, in EBL, due to the application of multiple electron beam lithography (MEBL) for throughput improvement, the features at boundaries of beams are susceptible to stitch errors.…”

Section: Dfm In Placementmentioning

confidence: 99%

Design for manufacturability and reliability in extreme-scaling VLSI

Roy

et al. 2016

Sci. China Inf. Sci.

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In the last five decades, the number of transistors on a chip has increased exponentially in accordance with the Moore's law, and the semiconductor industry has followed this law as long-term planning and targeting for research and development. However, as the transistor feature size is further shrunk to sub-14nm nanometer regime, modern integrated circuit (IC) designs are challenged by exacerbated manufacturability and reliability issues. To overcome these grand challenges, full-chip modeling and physical design tools are imperative to achieve high manufacturability and reliability. In this paper, we will discuss some key process technology and VLSI design co-optimization issues in nanometer VLSI.

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