2008 IEEE International Reliability Physics Symposium 2008

DOI: 10.1109/relphy.2008.4559009

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Simultaneous measurement of soft error rate of 90 nm CMOS SRAM and cosmic ray neutron spectra at the summit of Mauna Kea

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Tomomasa Uemura

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Real-time soft error testing system for large-area QDR II+ SRAM array on the Tibetan Plateau

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Microelectronics Reliability

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Real-time soft error testing system for large-area QDR II+ SRAM array on the Tibetan Plateau

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et al. 2019

Microelectronics Reliability

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Fast soft error rate computing technique based on state probability propagating

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2009

2009 4th IEEE Conference on Industrial Electronics and Applications

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Fast soft error sensitivity characterization technique is essential for the soft error tolerance optimization of modern VLSI circuits. In this paper, an efficient soft error evaluation technique based on syntax analysis and state probability propagating technique is developed, which can automatically analyze the soft error rate of combinational logic circuits and the combinational part of sequential circuits in verilog synthesized netlist within a few seconds. We implemented the idea in a software tool called HSECT-ANLY, which use verilog syntax analysis to automate the soft error rate evaluation procedure and state propagating technique to speed up the analyzation process. By using HSECT-ANLY, experiments are carried out on some ISCAS'85 and ISCAS'89 benchmark circuits implemented with TSMC 0.18 µm technology and results are obtained. The result comparison with the traditional test vector propagating technique shows that the introduced method is much faster (2-3 magnitudes speeding up) with some accuracy losses, and be very suitable for the reliability optimization as the sub-algorithm of the optimization algorithms such as genetic algorithms to evaluate the fitness (soft error rate) rapidly.

A review of real-time soft-error rate measurements in electronic circuits

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et al. 2012

2012 IEEE International Reliability Physics Symposium (IRPS)

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