Simultaneous Multi-Layer Access

Lee, Donghyuk; Ghose, Saugata; Pekhimenko, Gennady; Khan, Samira; Mutlu, Onur

doi:10.1145/2832911

Cited by 105 publications

(11 citation statements)

References 56 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This makes DRAM an increasingly significant system performance bottleneck today, especially for workloads with large footprints that are sensitive to DRAM access latency [12,77,111,112,. Therefore, there is significant opportunity for improving overall system performance by reducing the memory access latency [16,22,52,59,74,77,78,82,106,109,110,203,204]. Although conventional latencyhiding techniques (e.g., caching, prefetching, multithreading) can potentially help mitigate many of the performance concerns, these techniques (1) fundamentally do not change the latency of each memory access and (2) fail to work in many cases (e.g., irregular memory access patterns, random accesses, huge memory footprints).…”

Section: Slowdown Of Generational Improvementsmentioning

confidence: 99%

Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics

Patel

Kim

Shahroodi

et al. 2020

2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

Self Cite

View full text Add to dashboard Cite

Generational improvements to commodity DRAM throughout half a century have long solidified its prevalence as main memory across the computing industry. However, overcoming today's DRAM technology scaling challenges requires new solutions driven by both DRAM producers and consumers. In this paper, we observe that the separation of concerns between producers and consumers specified by industry-wide DRAM standards is becoming a liability to progress in addressing scaling-related concerns.To understand the problem, we study four key directions for overcoming DRAM scaling challenges using system-memory cooperation: (i) improving memory access latencies; (ii) reducing DRAM refresh overheads; (iii) securely defending against the RowHammer vulnerability; and (iv) addressing worsening memory errors. We find that the single most important barrier to advancement in all four cases is the consumer's lack of insight into DRAM reliability. Based on an analysis of DRAM reliability testing, we recommend revising the separation of concerns to incorporate limited information transparency between producers and consumers. Finally, we propose adopting this revision in a two-step plan, starting with immediate information release through crowdsourcing and publication and culminating in widespread modifications to DRAM standards.

show abstract

Section: Slowdown Of Generational Improvementsmentioning

confidence: 99%

Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics

Patel

Kim

Shahroodi

et al. 2020

2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

Self Cite

View full text Add to dashboard Cite

show abstract

“…Prior works show the applicability of different processing types in accelerating stencil computations: Near-Memory. PIMS [34] exploits the high-bandwidth provided by 3D-stacked memories (e.g., HMC [155], Hybrid Bandwidth Memory (HBM) [179,180]) to accelerate stencils. Casper, being a near-LLC accelerator, can be integrated with any commodity processor without the need of costly interfacing using through-silicon vias.…”

Section: Related Workmentioning

confidence: 99%

Casper: Accelerating Stencil Computations Using Near-Cache Processing

Denzler¹,

Oliveira²,

Hajinazar³

et al. 2023

IEEE Access

Self Cite

View full text Add to dashboard Cite

Stencil computations are commonly used in a wide variety of scientific applications, ranging from largescale weather prediction to solving partial differential equations. Stencil computations are characterized by three properties: (1) low arithmetic intensity, (2) limited temporal data reuse, and (3) regular and predictable data access pattern. As a result, stencil computations are typically bandwidth-bound workloads, which only experience limited benefits from the deep cache hierarchy of modern CPUs. In this work, we propose Casper, a near-cache accelerator consisting of specialized stencil computation units connected to the last-level cache (LLC) of a traditional CPU. Casper is based on two key ideas: (1) avoiding the cost of moving rarely reused data throughout the cache hierarchy, and (2) exploiting the regularity of the data accesses and the inherent parallelism of stencil computations to increase overall performance. With minimal changes in LLC address decoding logic and data placement, Casper performs stencil computations at the peak LLC bandwidth. We show that by tightly coupling lightweight stencil computation units near LLC, Casper improves performance of stencil kernels by 1.65× on average (up to 4.16×) compared to a commercial high-performance multi-core processor, while reducing system energy consumption by 35% on average (up to 65%). Casper provides 37× (up to 190×) improvement in performance-per-area compared to a state-of-the-art GPU.

show abstract

“…The novel 3D integration technique (Figure 5c) greatly promotes the fabrication of the IMC system. [75,76] IV. Architecture design and optimization: Reasonable architecture design and optimization are conductive to improving the efficiency of the whole computing system.…”

Section: Conclusion and Outlooksmentioning

confidence: 99%

“…The novel 3D integration technique (Figure 5c) greatly promotes the fabrication of the IMC system. [ 75,76 ] Architecture design and optimization: Reasonable architecture design and optimization are conductive to improving the efficiency of the whole computing system. Hence, it is necessary to design the system architecture according to the characteristics and requirements of the application.…”

Section: Conclusion and Outlooksmentioning

confidence: 99%

See 1 more Smart Citation

Functional Applications of Future Data Storage Devices

Yang

Zhou

Han

2021

Adv Elect Materials

View full text Add to dashboard Cite

traditional computing systems. Strategies like adopting multiple levels of cache, [3] increasing memory bandwidth, [4] and near-memory computing [5] have been proposed to alleviate this problem which yet still seem to be insufficient to meet the increasing computing demands.In-memory computing (IMC) which refers to the realization of computational tasks within the memory unit aims to reduce the frequent movement of data across the bus (Figure 1b), providing new insights for building highly efficient computing systems. IMC with function of parallel computation, reducing either the computational complexity or accessed amount of data effectively can be performed on both volatile and non-volatile memories. IMC has a wide range of applications, ranging from stochastic computing that requires randomness and low precision to scientific computing with high precision. Volatile memories including static randomaccess memory (SRAM) and dynamic random-access memory (DRAM) have been mainly utilized to execute Boolean functions and obtained dozens of times speedup in compute-heavy as well as low input-output movement applications compared with conventional architectures in which SRAM and DRAM were only used for data storage. [6] While nonvolatile memory including Flash and emerging memristive devices (resistive random-access memory [RRAM], phase-change memory [PCM], and magnetic random-access memory [MRAM], etc.) with the ability to store a continuous conductance state were proved to perform matrix-vector multiplication (MVM) for parallel IMC based on Ohm's law and Kirchhoff's law. [7] Especially, the memristive device with crossbar configuration can be directly integrated with high density local interconnects and low thermal burden, allowing the significant boost to IMC performance.This review provides an overview of related work in various memory techniques, their applications, and required parameters in IMC, the current state of the art, and evaluation metrics and highlights opportunities for further development. The Development of Memory TechnologiesDepending on the state of the data being stored, current memory technologies fall into two categories (Figure 2a): volatile and nonvolatile. Volatile memories will lose the data preserved when the power is disconnected, mainly including SRAM and DRAM, while information in nonvolatile memories including read-only memory (ROM), hard disk driver (HDD), Flash, MRAM, PCM, RRAM, and ferroelectric random-accessThe development of artificial intelligence and big data analytics is driving a revolution in methods for data processing and storage. Confronting speed and energy consumption issues, these fields require new computing systems to parallelly retrieve, process, and store massive amounts of data. Beyond CMOS devices and technology, advances in data storage technology such as static random-access memory, dynamic random-access memory, flash memories, resistive memories, phase change memories, and magnetic memories have made functional computing possible. In this article, a broad overvi...

show abstract

Simultaneous Multi-Layer Access

Cited by 105 publications

References 56 publications

Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics

Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics

Casper: Accelerating Stencil Computations Using Near-Cache Processing

Functional Applications of Future Data Storage Devices

Contact Info

Product

Resources

About