Simultaneously formed storage node contact and metal contact cell (SSMC) for 1 Gb DRAM and beyond

Lee, J.Y.; Kim, K.N.; Shin, Yokoyama; Lee, K.H.; Kim, J.S.; Kim, D.H.; Park, J.W.; Lee, J.G.

doi:10.1109/iedm.1996.554053

Cited by 7 publications

(5 citation statements)

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“…Process variation is a well-known phenomenon that introduces deviations between a chip's intended design and its actual implementation [13,37,60]. DRAM cells are affected by process variation in two major aspects: (i) cell capacitance and (ii) cell resistance.…”

Section: Process Variation: Cells Are Not Created Equalmentioning

confidence: 99%

“…First, due to process variation, some outlier cells suffer from a larger RC-delay than other cells, and require more time to be charged. For example, an outlier cell could have a very narrow connection (i.e., contact) to the bitline, which constricts the flow of charge and increases the RC-delay [37]. Second, due to temperature dependence, all cells suffer from a weaker charge-drive at high temperatures, and require more time to charge the bitline.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Adaptive-latency DRAM: Optimizing DRAM timing for the common-case

Lee

Kim

Pekhimenko

et al. 2015

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)

195

328

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In current systems, memory accesses to a DRAM chip must obey a set of minimum latency restrictions specified in the DRAM standard. Such timing parameters exist to guarantee reliable operation. When deciding the timing parameters, DRAM manufacturers incorporate a very large margin as a provision against two worst-case scenarios. First, due to process variation, some outlier chips are much slower than others and cannot be operated as fast. Second, chips become slower at higher temperatures, and all chips need to operate reliably at the highest supported (i.e., worst-case) DRAM temperature (85• C). In this paper, we show that typical DRAM chips operating at typical temperatures (e.g., 55• C) are capable of providing a much smaller access latency, but are nevertheless forced to operate at the largest latency of the worst-case.Our goal in this paper is to exploit the extra margin that is built into the DRAM timing parameters to improve performance. Using an FPGA-based testing platform, we first characterize the extra margin for 115 DRAM modules from three major manufacturers. Our results demonstrate that it is possible to reduce four of the most critical timing parameters by a minimum/maximum of 17.3%/54.8% at 55• C without sacrificing correctness. Based on this characterization, we propose Adaptive-Latency DRAM (AL-DRAM), a mechanism that adaptively reduces the timing parameters for DRAM modules based on the current operating condition. AL-DRAM does not require any changes to the DRAM chip or its interface.We evaluate AL-DRAM on a real system that allows us to reconfigure the timing parameters at runtime. We show that AL-DRAM improves the performance of memory-intensive workloads by an average of 14% without introducing any errors. We discuss and show why AL-DRAM does not compromise reliability. We conclude that dynamically optimizing the DRAM timing parameters can reliably improve system performance.

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Section: Process Variation: Cells Are Not Created Equalmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Adaptive-latency DRAM: Optimizing DRAM timing for the common-case

Lee

Kim

Pekhimenko

et al. 2015

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)

195

328

View full text Add to dashboard Cite

show abstract

“…In practice, however, there is a very large margin in the timing parameters to ensure correct operation under worst-case conditions with respect to two aspects. First, due to process variation, some outlier cells su er from a larger RC-delay than other cells [64,94], and require more time to be accessed. Second, due to temperature dependence, DRAM cells lose more charge at high temperature [97,171], and therefore require more time to be accessed.…”

Section: Problem: High Dram Latencymentioning

confidence: 99%

Adaptive-Latency DRAM: Reducing DRAM Latency by Exploiting Timing Margins

Lee¹,

Kim²,

Pekhimenko³

et al. 2018

Preprint

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“…In practice, however, there is a very large margin in the timing parameters to ensure correct operation under worst-case conditions with respect to two aspects. First, due to process variation, some outlier cells suffer from a larger RC-delay than other cells [46,67], and require more time to be accessed. Second, due to temperature dependence, DRAM cells lose more charge at high temperature [124], and therefore require more time to be sensed and restored.…”

Section: Summary 1problem: High Dram Latencymentioning

confidence: 99%

Adaptive-Latency DRAM (AL-DRAM)

Lee¹,

Kim²,

Pekhimenko³

et al. 2016

Preprint

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This paper summarizes the idea of Adaptive-Latency DRAM (AL-DRAM), which was published in HPCA 2015 [64]. The key goal of AL-DRAM is to exploit the extra margin that is built into the DRAM timing parameters to reduce DRAM latency. The key observation is that the timing parameters are dictated by the worst-case temperatures and worst-case DRAM cells, both of which lead to small amount of charge storage and hence high access latency. One can therefore reduce latency by adapting the timing parameters to the current operating temperature and the current DIMM that is being accessed. Using an FPGA-based testing platform, our work first characterizes the extra margin for 115 DRAM modules from three major manufacturers. The experimental results demonstrate that it is possible to reduce four of the most critical timing parameters by a minimum/maximum of 17.3%/54.8% at 55 • C while maintaining reliable operation. AL-DRAM adaptively selects between multiple different timing parameters for each DRAM module based on its current operating condition. AL-DRAM does not require any changes to the DRAM chip or its interface; it only requires multiple different timing parameters to be specified and supported by the memory controller. Real system evaluations show that AL-DRAM improves the performance of memory-intensive workloads by an average of 14% without introducing any errors [64].

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Simultaneously formed storage node contact and metal contact cell (SSMC) for 1 Gb DRAM and beyond

Cited by 7 publications

References 0 publications

Adaptive-latency DRAM: Optimizing DRAM timing for the common-case

Adaptive-latency DRAM: Optimizing DRAM timing for the common-case

Adaptive-Latency DRAM: Reducing DRAM Latency by Exploiting Timing Margins

Adaptive-Latency DRAM (AL-DRAM)

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