Single-chip 4×500-MBd CMOS transceiver

Widmer, A.X.; Wrenner, K.R.; Ainspan, H.; Parker, B.; Austruy, P.; Brezzo, Bernard; Haen, A.-M.; Ewen, J.F.; Soyuer, M.; Blanc, A.; Abbiate, J.-C.; Deutsch, A.; Shin, Hyun Jang

doi:10.1109/4.545824

Cited by 7 publications

(4 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Note in Table 2 that the total cable attenuation at 1 GHz for the three cases shown, for lengths of 2, 2, and 0.5 m, respectively, are 2-4 dB, which is a substantial amount of loss since a typical path of the type shown in Fig. 2(a) could have total loss of about 7 dB [28] and cable lengths could be 5-10 m.…”

Section: A High-performance High-density Cablesmentioning

confidence: 98%

“…What is of significance is tight signal integrity control. Generally, a 40-50% loss of the eye opening (40-50% of the available swing at the driver circuit output) or the area of the waveform in a predetermined "eye mask" (a time and amplitude window during the cycle time when data are being sampled) is associated with a reasonable minimum signal at the receiver to overcome all the noise sources discussed earlier [28], [29]. For a 500-Mb/s data rate, for example, a 2-ns-wide clean data interval has to be assured (4-ns repetition rate) while the path delay might be 10-20 ns.…”

Section: E Signal Integritymentioning

confidence: 99%

See 1 more Smart Citation

Electrical characteristics of interconnections for high-performance systems

Deutsch

1998

Proc. IEEE

Self Cite

152

View full text Add to dashboard Cite

A review is presented of the electrical characteristics of highdensity, high-performance interconnections used in digital and communication applications. These interconnections behave as lossy transmission lines for the frequency range of interest. A brief theoretical explanation of the key properties of lossy, coupled transmission lines is given. A new short-pulse propagation technique used for characterizing a large category of wiring is described. A detailed description is made of each of the major interconnect types encountered, namely, shielded cables, printed circuit boards, ceramic carriers, thin-film wiring, and on-chip wiring. Representative examples are given in each case to highlight the key performance-limiting parameters. The modeling and measurement techniques used are explained and examples are given. Future technological directions and their effect on performance are discussed.

show abstract

Section: A High-performance High-density Cablesmentioning

confidence: 98%

Section: E Signal Integritymentioning

confidence: 99%

Electrical characteristics of interconnections for high-performance systems

Deutsch

1998

Proc. IEEE

Self Cite

152

View full text Add to dashboard Cite

show abstract

“…TX data can be a (2 32 -1) bit PRBS or an externally loaded 140-bit pattern which subsequently passes through a bypass-able 8B/10B encoder. Two TX designs were implemented: the low-power TX with 2-tap equalized voltagemode (V-mode) driver [1], and the high-performance TX with 2-way interleaved 2 to 6-tap programmable MAC (multiplyaccumulate) based FIR TX equalizers and a 6-bit DAC currentmode (I-mode) driver [2]. Both support swings up to 600mV.…”

Section: Introductionmentioning

confidence: 99%

Power/Performance/Channel Length Tradeoffs in 1.6 to 9.6Gbps I/O Links in 90nm CMOS for Server, Desktop, and Mobile Applications

Yeung

Canagasaby

Tripathi

et al.

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.

View full text Add to dashboard Cite

Performance and power of 1.6 to 9.6Gbps server, desktop, and mobile I/O links in a 1.2V 90nm CMOS test chip implementing equalized voltage-mode and current-mode drivers, TX and RX equalizers, self-biased ring oscillator and LC PLLs, and different RX clocking schemes are compared. The novel combination of voltage-mode driver (equalized or unequalized) and RX equalizer delivers the lowest power (12.1mW/Gbps at 7.2Gbps), offering a low-power option for short-distance links. (Keywords: low power, I/O link, equalizer, voltage-mode driver) IntroductionThe 3 key metrics in Gigabit I/O designs are performance (data rate), power, and channel length. Different tradeoffs are made depending on system requirements. In server interconnections, the major challenge is to overcome the harsh channel conditions. Sophisticated equalizers are implemented to increase the data rate and distance at the expense of increased power. On the other hand, I/Os for desktop and mobile systems need cheaper cooling solutions, making power optimization the most important design metric. This is especially true for mobile I/Os, where the power is further limited by battery capacities.Transceiver System A high-speed transceiver test chip containing I/O links for server, desktop, and mobile applications was implemented in a 1.2V, 90nm digital CMOS process. The chip contains 2 I/O ports on the 2 sides of a 5mm x 5mm die, with shared circuitry and digital blocks situated in the middle, as shown in Figure 1. Two packages, a land-grid array and a ball-grid array, allow the packaged chip to be placed in a socket or soldered directly on a test board. Figure 2 shows the architecture of each port, which contains 6 differential data lanes and 1 differential clock lane. A halfrate TxClk is generated by a TxPLL, which can be an LC-PLL or a self-biased ring oscillator PLL (SBRO-PLL) shared between the ports, and distributed to all I/Os using CMOS buffers. TX data can be a (2 32 -1) bit PRBS or an externally loaded 140-bit pattern which subsequently passes through a bypass-able 8B/10B encoder. Two TX designs were implemented: the low-power TX with 2-tap equalized voltagemode (V-mode) driver [1], and the high-performance TX with 2-way interleaved 2 to 6-tap programmable MAC (multiplyaccumulate) based FIR TX equalizers and a 6-bit DAC currentmode (I-mode) driver [2]. Both support swings up to 600mV.At RX, a DLL generates 8 global clock phases at 45 o spacings from a half-rate forwarded clock or a SBRO-PLL (labeled RxPLL) locked to a reference (local) clock. The clock phases are distributed to all I/Os where they are phase multiplexed and interpolated to generate the skewed RxClks.

show abstract

“…24 Regenerated data at 1.1Gbps, 60°C 51Figure 9.25 Configuration 1 for testing the impulse capture range 52Figure 9.26 Step control voltage at 25 °C viii 27 DFT of the recovered clocks at 25°C 53 29 DFT of the recovered clocks at 60°C 54 34 DFT of the recovered clocks at 60°C Figure 9.35 Control voltage at 25 °C Figure 9.36 DFT of the clocks at the highest and lowest Frequency Figure 9.37 Time piece at the lowest frequency, 25°C 38 Time piece at the highest frequency, 25°C 40 DFT of the clocks at the highest and lowest frequency 41 Time piece at the lowest frequency, 60°C 60 42 Time piece at the highest frequency, 60°C 60…”

mentioning

confidence: 99%

CMOS circuits for high speed serial data communication

View full text Add to dashboard Cite

With the fast growth of computer power and network services, high performance peripherals and interfaces are being developed to meet the system needs. High speed serial data communication devices are especially important and much effort has been spent to increase the bandwidth, reduce the cost, lower the power dissipation and improve the level of integration. Driven by these motivations, various commercial products with data rates ranging from several hundred Mbps to several Gbps have been developed in GaAs or Si bipolar technologies. Potentially less expensive silicon CMOS implementation of these functions are presently begin investigated and is the focus of this work. The serial data link has been dominant in network connections, such as Ethernet, FDDI or ATM, and will find even wider application in the future. This work focuses on the implementation of some basic building blocks for very high speed serial data communication using CMOS technology. At the transmitter end, a novel parallel-toserial converter is presented, whose core is a 5 by 4 register matrix which combines the selection and shift schemes for conversion. Using this architecture, a pipelined data loading is applied to multiple data paths running at sub-multiple of the data rate. This significantly reduces the dynamic power dissipation and eases the system design. The special clock strategy to drive the converter is investigated in this work. SPICE simulations and a chip layout of this method are presented. Various design and layout considerations are also discussed. At the receiver end, a clock recovery circuit based on a charge pump phase locked loop is proposed. The VCO has an internal feedback loop to adjust the duty cycle at different frequency. A simple conventional phase detector with a limited output swing is used to achieve the high working frequency. A modified symmetrical charge pump circuit improves linearity of the output current versus the input UP and DOWN signal. Some characteristics such as impulse capture range and xi lock range are estimated from the simulations. All the designs assume 0.5 ~m singlepoly triple-metal CMOS technology. This work presents an analysis to the system as well as individual parts and explores the possibility of CMOS solutions for gigabit data communication. It could be used or adopted in future designs in similar applications.

show abstract

Single-chip 4×500-MBd CMOS transceiver

Cited by 7 publications

References 8 publications

Electrical characteristics of interconnections for high-performance systems

Electrical characteristics of interconnections for high-performance systems

Power/Performance/Channel Length Tradeoffs in 1.6 to 9.6Gbps I/O Links in 90nm CMOS for Server, Desktop, and Mobile Applications

CMOS circuits for high speed serial data communication

Contact Info

Product

Resources

About