Ewen et al. (54) (75) (73) (21) 22) (51) 52 58)

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This work implements the media independent functions specified in the emerging ANSI fibre channel standard at 1062.5Mbaud. Integrated onto a single CMOS chip are: two phase-locked loops (PLL) for clockgeneration and clockrecovery, a selectable 1B or 2B parallel interface with corresponding multiplexer and demultiplexer for parallel-to-serial and serial-to-parallel conversion, word alignment logic for byte synchronization, 8B/10B coder and decoder, and high-speed differential CMOS PECL drivers and receivers for the serial I/O. The chip measures 3.9 x4.5mm2with 100 I/O and dissipates 1.2W at 1062Mbaud with a 3.6V supply. This design achieves higher-speed operation than previous CMOS work with similar integration, and lower power dissipation with higher integration than bipolar implementations at comparable speeds. [l, 21

The functional characteristics and design challenges associated with a variety of communication-related circuits are presented. These include the mixed-signal design and noise issues associated with high-speed clock generation and recovery for serial data communication. Hardware results are presented on the noise properties of common integrated voltage-controlled oscillator (VCO) circuits. introductionA key characteristic of ICs in many communication-related applications is the combination of analog circuits with digital logic, while maintaining maximum performance at minimum power and cost. This combination presents a number of challenges beyond basic circuit design issues, ranging from technology choice and simulation techniques to noise and crosstalk. This paper focuses on recent CMOS design work addressing these issues, with specific attention to the area of high-speed serial data communication.Serial baseband data links, whether using fiber-optic or coaxial cables, incorporate coders and decoders, highspeed multiplexors and demultiplexors, and low-speed clock synchronization, along with phase-locked loops for

No abstract