Single crystal hybrid perovskite field-effect transistors

Abstract

The fields of photovoltaics, photodetection and light emission have seen tremendous activity in recent years with the advent of hybrid organic-inorganic perovskites. Yet, there have been far fewer reports of perovskite-based field-effect transistors. The lateral and interfacial transport requirements of transistors make them particularly vulnerable to surface contamination and defects rife in polycrystalline films and bulk single crystals. Here, we demonstrate a spatially-confined inverse temperature crystallization strategy which synthesizes micrometre-thin single crystals of methylammonium lead halide perovskites MAPbX3 (X = Cl, Br, I) with sub-nanometer surface roughness and very low surface contamination. These benefit the integration of MAPbX3 crystals into ambipolar transistors and yield record, room-temperature field-effect mobility up to 4.7 and 1.5 cm2 V−1 s−1 in p and n channel devices respectively, with 104 to 105 on-off ratio and low turn-on voltages. This work paves the way for integrating hybrid perovskite crystals into printed, flexible and transparent electronics.

Asymmetric Contact‐Induced Self‐Driven Perovskite‐Microwire‐Array Photodetectors

“…Therefore, the resultant built-in potential in the device channel is determined by the Schottky barrier height difference between two opposite MW-metal contacts. [41] As a result, a built-in potential with the direction from MW (Ag) to Au (MW) is formed near the MW-Au (MW-Ag) contact. In this case, the photocarriers (induced by light absorption with a photon energy higher than perovskite bandgap) have no preferred drift direction in the channel, or in other words, the photocurrent is opposite and antisymmetric near both MW-metal contacts, leading to zero net photocurrent.…”

Application of Perovskite‐Structured Materials in Field‐Effect Transistors

“…Thin-Film: CH 3 NH 3 PbI 3−x Cl x [32,33,104,105,110,111,113,[120][121][122] has been investigated as semiconductor in FETs. Chin et al [102] fabricated a FET by using CH 3 NH 3 PbI 3 as channel and 500 nm SiO 2 layer as the dielectric layer.…”

“…The transport was limited by ion migration caused by point defects and grain boundaries, the polarization disorder of the MA + cations, and the thermal vibrations of the lead halide inorganic cages. [108] Yu et al [113] demonstrated a FET device based on micrometer-thin MAPbX 3 (X = Cl, Br, I) single crystal as the semiconductor. In PEIE-treated devices, the electron mobility values reached 5 cm 2 V −1 s −1 at 100 K and 3 cm 2 V −1 s −1 at room temperature.…”

“…The room temperature electron mobility was improved from 0.02 ± 0.01 cm 2 V −1 s −1 for bare Au contacts to 0.1-0.5 cm 2 V −1 s −1 for polyethyleneimine ethoxylated (PEIE)treated electrodes. [113] Various Dielectric Layers: SiO 2 normally serves as the dielectric layer in CH 3 NH 3 PbI 3 -based FETs. [107] The hysteresis was suppressed by optimizing the thin film microstructure and source-drain contact.…”

“…Equal hole and electron mobilities of 10 cm 2 V −1 s −1 was achieved at room temperature, which is owing to large grain size and passivation of grain boundaries by the formation of solvent complexes. [32,104,107,[109][110][111]113,121,122] The extracted mobility would fluctuate significantly based on measurement conditions, such as sweeping direction and sweeping rate. The FET devices were fabricated by using individual CH 3 NH 3 PbI 3 microplates as the semiconducting layer, two prefabricated Cr/Au electrodes as the source-drain, and 300 nm SiO 2 as gate dielectric layer.…”