Single-crystalline silicon nanomembrane thin-film transistors with anodized aluminum oxide as a gate dielectric on rigid and flexible substrates

Abstract

Flexible integrated circuits (ICs) have gained a lot of attentions in recent years for their emerging application in wearable electronics. Flexible thin-film transistors (TFTs) with low-cost and high-performance are highly desirable as essential and fundamental element for most of the flexible applications. In this paper, we fabricated single-crystalline silicon nanomembrane (SiNM) based TFTs with anodized aluminum oxide (AAO) as dielectric material on glass and flexible plastic substrates. Good quality AAO was obtained on plastic substrates at room temperature. AFM was used for surface morphology of AAO gate dielectric layers on different substrates (i.e. glass, polyethylene terephthalate (PET) and SU-8 coated PET). The electrical characteristics of the AAO gate dielectric layers on different substrates were also analyzed with metal- dielectric-metal (MIM) capacitors. SiNMs were processed with complementary metal oxide semiconductor (CMOS) compatible semiconductor process (e.g. photolithography, ion implantation, thermal annealing, reactive ion etching, metal evaporation, etc.), and then transferred to the substrates with AAO/aluminum stack layers. Performances of transistors on glass and plastic substrates were characterized. Compared with the TFT fabricated on glass substrate, TFT fabricated directly on a PET substrate have lower performance due to poor surface roughness. For optimization of the surface roughness, PET was modified with coating SU-8 photoresist. By this way, TFT had properties close to that on glass substrate. AAO that can be manufactured at room temperature provides a simple and low-cost solution for high-performance flexible single-crystalline SiNM TFTs.

Flexible Hybrid Single-Crystalline Silicon Nanomembrane Thin-Film Transistor with Organic Polymeric Polystyrene as a Gate Dielectric on a Plastic Substrate

“…The maximum transconductance reached ∼6.5 μS at an applied gate voltage of ∼1.35 V. During the annealing process, the effective distance between the doped regions ( L ) may become slightly smaller than 4 μm (∼3.8 μm) because of ion diffusion. , Therefore, the calculated mobility taking into account the diffusion effect should be appropriate according to the equation where C ox is the quasi-static unit-area capacitance of the gate dielectric. The effective channel electron mobility was calculated to be ∼120 cm 2 V –1 S –1 , comparable to those of SiNM TFTs based on inorganic dielectrics ,, and much higher than those of TFTs based on amorphous, polycrystalline, and organic semiconductors. − ,− An ∼250 mV/dec subthreshold swing (SS) was also calculated by the equation which indicated that the TFT can operate at high speed in the subthreshold region. The interfacial trap density ( D it ) can be obtained through the equation where k is the Boltzmann constant, T is the absolute temperature, q is the unit electron charge, and C ox is the quasi-static unit-area capacitance of the gate dielectric.…”

“…where C ox is the quasi-static unit-area capacitance of the gate dielectric. The effective channel electron mobility was calculated to be ∼120 cm 2 V −1 S −1 , comparable to those of SiNM TFTs based on inorganic dielectrics 40,50,51 and much higher than those of TFTs based on amorphous, polycrystalline, and organic semiconductors.…”

“…were first finished on the SOI wafer. The detailed methods are provided in previous works. , For the fabrication of dielectric/gate (PS/ITO) layers on the PET substrate, ∼100 nm ITO as a gate electrode was first deposited using magnetron sputtering on a 175 μm PET substrate. An ∼5 Ω/cm electrical resistivity of the ITO layer was determined.…”

“…The interfacial trap density was calculated to be as low as ∼2.06 × 10 12 eV −1 cm −2 , comparable to those of SiNM TFTs fabricated with clean and smooth dielectric surfaces by using a transfer process. 40,46 The PS dielectric layer has the merits of good roughness and cleanliness because fewer impurities and suspension bonds were introduced at the SiNM/PS interface, which resulted in a low level of the interface states. 40,52 Transfer characteristic enabled dual-direction sweeping showed a low hysteresis level (Figure S1).…”

“…40,46 The PS dielectric layer has the merits of good roughness and cleanliness because fewer impurities and suspension bonds were introduced at the SiNM/PS interface, which resulted in a low level of the interface states. 40,52 Transfer characteristic enabled dual-direction sweeping showed a low hysteresis level (Figure S1). This also implied a less effective interface charge of the SiNM/PS hybrid TFT, which was consistent with the calculated low interfacial trap density.…”