Single-Cycle Implementations of Block Ciphers

Maene, Pieter; Verbauwhede, Ingrid

doi:10.1007/978-3-319-29078-2_8

Cited by 31 publications

(20 citation statements)

References 26 publications

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“…Although AES is used in COPA's original design, our implementation uses PRINCE [3], which is highly efficient [16]. We placed two pipeline registers inside our PRINCE implementation to allow the MAC verification component to meet the timing constraint of 100 MHz (see Section 5.2).…”

Section: Mac Verificationmentioning

confidence: 99%

“…We placed two pipeline registers inside our PRINCE implementation to allow the MAC verification component to meet the timing constraint of 100 MHz (see Section 5.2). A three cycle implementation of AES will likely have a huge overhead in terms of area and delay, as observed by [16] in a comparison of single cycle implementations. PRINCE's 64-bit block size allows for more effective use of the Zynq's 64-bit HP0 port, since memory blocks received from HP0 can immediately be processed by our MAC primitive.…”

Section: Mac Verificationmentioning

confidence: 99%

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SCM

Clercq

Keulenaer

Maena

et al. 2017

Proceedings of the 2017 ACM on Asia Conference on Computer and Communications Security

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An increasing number of applications implemented on a SoC (System-on-chip) require security features. This work addresses the issue of protecting the integrity of code and read-only data that is stored in memory. To this end, we propose a new architecture called SCM, which works as a standalone IP core in a SoC. To the best of our knowledge, there exists no architectural elements similar to SCM that offer the same strict security guarantees while, at the same time, not requiring any modifications to other IP cores in its SoC design. In addition, SCM has the flexibility to select the parts of the software to be protected, which eases the integration of our solution with existing software. The evaluation of SCM was done on the Zynq platform which features an ARM processor and an FPGA. The design was evaluated by executing a number of different benchmarks from memory protected by SCM, and we found that it introduces minimal overhead to the system.

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Section: Mac Verificationmentioning

confidence: 99%

Section: Mac Verificationmentioning

confidence: 99%

SCM

Clercq

Keulenaer

Maena

et al. 2017

Proceedings of the 2017 ACM on Asia Conference on Computer and Communications Security

Self Cite

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“…In order to prevent tampered instructions from executing, MAC computation needs to occur in only a few cycles. Therefore, the cipher was unrolled to require only two cycles for each operation [36]. This reduces the maximum clock frequency of the processor, as the block cipher increases the critical path of the processor.…”

Section: Methodsmentioning

confidence: 99%

SOFIA: Software and control flow integrity architecture

Clercq

Götzfried

Übler

et al. 2017

Computers & Security

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Abstract-Microprocessors used in safety-critical systems are extremely sensitive to software vulnerabilities, as their failure can lead to injury, damage to equipment, or environmental catastrophe. This paper proposes a hardware-based security architecture for microprocessors used in safety-critical systems. The proposed architecture provides protection against code injection and code reuse attacks. It has mechanisms to protect software integrity, perform control flow integrity, prevent execution of tampered code, and enforce copyright protection. We are the first to propose a mechanism to enforce control flow integrity at the finest possible granularity. The proposed architectural features were added to the LEON3 open source soft microprocessor, and were evaluated on an FPGA running a software benchmark. The results show that the hardware area is 28.2% larger and the clock is 84.6% slower, while the software benchmark has a cycle overhead of 13.7% and a total execution time overhead of 110% when compared to an unmodified processor.

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“…Lightweight block ciphers can be implemented at lower cost while maintaining the same or better circuit size, power consumption, and latency as conventional standard encryption AES. PRINCE 6,7 is a lightweight block cipher with excellent circuit size and latency. PRINCE has a high overall reputation for circuit size, processing speed, and peak power in comparison with other ciphers 4 in unrolled architecture implementation in which all cryptographic circuits are composed of combinational circuits.…”

Section: Introductionmentioning

confidence: 99%

Multiple countermeasures on unrolled architecture PRINCE against power analysis and its evaluation

Takemoto

Nozaki

Yoshikawa

2020

Elect Comm in Japan

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Lightweight block ciphers, which can be implemented with low cost, are suitable for improving the safety of small devices. PRINCE is a typical lightweight block cipher and suitable for unrolled architecture implementation. In addition, PRINCE can be achieved low latency and embedded in a small area. However, it has been reported that PRINCE with unrolled architecture implementation is vulnerable to power analysis. Regarding countermeasure against power analysis, the threshold implementation and rotating S‐boxes masking are popular countermeasures, these require large implementation overhead though. Therefore, this study proposes a low‐overhead power analysis countermeasure method for PRINCE with unrolled architecture. Moreover, evaluation experiments using a field‐programmable gate array verify the effectiveness of the proposed method. In experiments, the proposed method improved tamper resistance and reduced implementation overhead in comparison with the conventional method.

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Single-Cycle Implementations of Block Ciphers

Cited by 31 publications

References 26 publications

SCM

SCM

SOFIA: Software and control flow integrity architecture

Multiple countermeasures on unrolled architecture PRINCE against power analysis and its evaluation

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