Single-Electron Arithmetic Circuits for Sigma-Delta Domain Signal Processing

Katao, T.; Suzuki, Y.; Fujisaka, Hisato; Kamio, Takeshi; Ahn, Chang-Jun; Haeiwa, Kazuhisa

doi:10.1109/nano.2008.219

Cited by 5 publications

(6 citation statements)

References 6 publications

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“…5(a), . Then, the range of is (17) The necessary number of sorter outputs to represent is (18) The sorter inputs are input consisting of input bits , integrator output represented by sorter outputs, and the -bit negative feedback signal. Taking -bit cancellation between and the negative feedback signal into account, we calculate the size, or the necessary number of input terminals, of a sorting network for first-order multi-level SD modulation to be (19) Then, the sorting network has upper and lower sets of unconnected binary outputs.…”

Section: Digital Sigma-delta Modulationmentioning

confidence: 99%

Sorter-Based Arithmetic Circuits for Sigma-Delta Domain Signal Processing—Part I: Addition, Approximate Transcendental Functions, and Log-Domain Operations

Fujisaka

Kamio

Ahn

et al. 2012

IEEE Trans. Circuits Syst. I

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We construct arithmetic modules for signal processing with sigma-delta modulated signal form which has advantage in signal quality over other pulsed signal forms. In the first part of this paper, adders and exponential function modules are presented first and secondly. By utilizing the two modules, several transcendental functions including hyperbolic and logarithmic functions are constructed. The exponential functions and logarithmic functions provide log-domain arithmetic operations including multiplication, division, and power functions. Only two bit-manipulations, bit-permutation with sorting networks and bit-reversal with NOT gates, have built up all the arithmetic operations on any form of sigma-delta modulated signals. These modules, together with algebraic functions to be presented in the second part of this paper, organize an extensive module library for the sigma-delta domain signal processing.

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Section: Digital Sigma-delta Modulationmentioning

confidence: 99%

Sorter-Based Arithmetic Circuits for Sigma-Delta Domain Signal Processing—Part I: Addition, Approximate Transcendental Functions, and Log-Domain Operations

Fujisaka

Kamio

Ahn

et al. 2012

IEEE Trans. Circuits Syst. I

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“…and an output of a multiplier archetype are -level signals represented by bit-streams, , , , , the output average should be (3) Then, multiplier archetypes consist of exclusive-NOR functions and -level adders presented in Section III of Part I for summing the exclusive-NOR outputs.…”

Section: When Multiple Inputsmentioning

confidence: 99%

“…Fig. 24 shows a first-order 2-input binary Type-I adder built of the three kinds of circuit cells [3], [4]. The adder consists of 63 SET junctions.…”

Section: A Circuit Modules Constructed Of Set Junctionsmentioning

confidence: 99%

Sorter-Based Arithmetic Circuits for Sigma-Delta Domain Signal Processing—Part II: Multiplication and Algebraic Functions

Fujisaka

Sakamoto

Ahn

et al. 2012

IEEE Trans. Circuits Syst. I

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We construct arithmetic modules for signal processing with sigma-delta modulated signal form which has advantage in signal quality over other pulsed signal forms. In the second part of this paper, multi-input multipliers are presented first. Secondly, dividers and square root function modules with the multiplier on their internal feedback path are constructed. Combined use of the multipliers, dividers, and the square root functions creates various algebraic functions including polynomial and rational functions. Only two bit-manipulations, bit-permutation with sorting networks and bit-reversal with NOT gates, have built up all the algebraic operations on any form of SD modulated signals. These modules, together with transcendental functions presented in the first part of this paper, organize an extensive module library for the sigma-delta domain signal processing. The multiplier output contains noise components which originate from quantization. The noise power can decrease in exchange for circuit complexity. A time-division multiplexing technique based on N-tone sigma-delta modulation is applied to the multipliers for reducing the complexity. Signal processing circuits built of nanometer-scale quantum effect devices must be equipped with fault tolerance of transient device error. By computer simulation of a multiplier built of single-electron tunneling devices, we found that the multiplier decreased its output SNDR from 43 to 27dB at an OSR of as the device error rate increased from 0 to . However, the multiplier was never functionally failed during the simulation.

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“…Then, the output can be Fig. 18 shows an adder built of the SET gates introduced in section 4 (Katao et al, 2008). Table 2.…”

Section: Addermentioning

confidence: 99%

“…(20), the multiplier is built of SET gates as shown in Fig. 20 (Katao et al, 2008). (Wasshuber et al, 1997).…”

Section: Multipliermentioning

confidence: 99%

Single-Electron Circuits for Sigma-Delta Domain Signal Processing

Fujisaka¹

2010

Cutting Edge Nanotechnology

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Single-Electron Arithmetic Circuits for Sigma-Delta Domain Signal Processing

Cited by 5 publications

References 6 publications

Sorter-Based Arithmetic Circuits for Sigma-Delta Domain Signal Processing—Part I: Addition, Approximate Transcendental Functions, and Log-Domain Operations

Sorter-Based Arithmetic Circuits for Sigma-Delta Domain Signal Processing—Part I: Addition, Approximate Transcendental Functions, and Log-Domain Operations

Sorter-Based Arithmetic Circuits for Sigma-Delta Domain Signal Processing—Part II: Multiplication and Algebraic Functions

Single-Electron Circuits for Sigma-Delta Domain Signal Processing

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