Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist

Tu, Ming-Hsien; Lin, Jihi-Yu; Tsai, Ming-Chien; Jou, Shyh-Jye; Chuang, Ching-Te

doi:10.1109/tcsi.2010.2071690

Cited by 122 publications

(41 citation statements)

References 20 publications

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“…Expect that "1" is set with "0" and at the same time at first (1) will be saved in node A. N1 and P1 need aid to be measured such that node A may be pulled down enough will transform P2 to on condition. This in-turn changes node B on a chance to be pulled up condition [5][6]. Those cross coupled inverter pair need to have higher gain and causes nodes with switch on inverse voltages.…”

Section: Transistor Memory Cellmentioning

confidence: 99%

A Novel concept on 8-Transistor Dynamic Feedback Control on Static RAM Cell Array

Renukarani¹,

Godavarthi²,

Roshini³

et al. 2018

IJET

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A novel idea of 8-Transistor (8T) static random access memory cell with enhanced information stability, sub threshold operation may be outlined. Those prescribed novel built single-ended for dynamic control 8 transistors static RAM (SRAM) cell enhances the static noise margin (SNM) to grater low energy supply. The suggested 8T takes less read and write power supply compared to 6T. Those suggested 8T need higher static noise margin than that from 6T. The portable microprocessor chips need ultralow energy consuming circuits on use battery to more drawn out span. The power utilization might be minimized utilizing non-conventional gadget structures, new circuit topologies, and upgrading the architecture. Although, voltage scaling require of the operation completed over sub threshold for low power consumption, and there will be an inconvenience from exponential decrease in execution. However, to sub threshold regime, that data stability of SRAM cell might a chance to be a amazing issue and worsens for those scaling from claming MOSFET ought to subnanometer engineering technology.

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Section: Transistor Memory Cellmentioning

confidence: 99%

A Novel concept on 8-Transistor Dynamic Feedback Control on Static RAM Cell Array

Renukarani¹,

Godavarthi²,

Roshini³

et al. 2018

IJET

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show abstract

“…Using this concept, researchers [89][90][91][92][93][94] have proposed the subthreshold SRAM cells to reduce the overall power consumption in the cell. Teman et al [95] have designed a robust, low-voltage SRAM bit cell with reduced 5 transistors compared to the standard 6T circuit.…”

Section: Subthreshold Sram Cellmentioning

confidence: 99%

Power Efficient Data-Aware SRAM Cell for SRAM-Based FPGA Architecture

Singh¹

2017

Field - Programmable Gate Array

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The design of low-power SRAM cell becomes a necessity in today's FPGAs, because SRAM is a critical component in FPGA design and consumes a large fraction of the total power. The present chapter provides an overview of various factors responsible for power consumption in FPGA and discusses the design techniques of low-power SRAMbased FPGA at system level, device level, and architecture levels. Finally, the chapter proposes a data-aware dynamic SRAM cell to control the power consumption in the cell. Stack effect has been adopted in the design to reduce the leakage current. The various peripheral circuits like address decoder circuit, write/read enable circuits, and sense amplifier have been modified to implement a power-efficient SRAM-based FPGA.

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“…Data is written from bit line to on the node 'Q' through the wwL. Due to separate word lines data is stability is improved 18 . The chance of data distortion is eliminated by keeping CS turned off.…”

Section: Write Operationmentioning

confidence: 99%

A New 8T SRAM Circuit with Low Leakage and High Data Stability Idle Mode at 70nm Technology

2017

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Memory has been facing several problems in which the leakage current is the most severe. Many techniques have been proposed to withstand leakage control such as power gating and ground gating. In this paper a new 8T SRAM cell, which adopts a single bit line scheme has been proposed to limit the leakage current as well as to gain high hold static noise margin. The proposed cell with low threshold voltage, high threshold voltage and dual threshold voltage are used to effectively reduce leakage current, and delay. Additionally, the comparison has been performed between conventional 6T SRAM cell and the new 8T SRAM cell. The proposed circuit consumes 671.22 pA leakage current during idle state of the circuit which is very less as compare to conventional 6T SRAM cell with sleep and hold transistors and with different b ratio. The proposed new 8T SRAM cell shows highest noise immunity 0.329mv during hold state. Furthermore, the proposed new 8T SRAM circuit represents minimum read and write access delays 114.13ps and 38.56ps respectively as compare to conventional 6T SRAM cell with different threshold voltages and b ratio.keywords: SRAM, static noise margin, single bit line, threshold voltage, leakage current, b ratio.

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Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist

Cited by 122 publications

References 20 publications

A Novel concept on 8-Transistor Dynamic Feedback Control on Static RAM Cell Array

A Novel concept on 8-Transistor Dynamic Feedback Control on Static RAM Cell Array

Power Efficient Data-Aware SRAM Cell for SRAM-Based FPGA Architecture

A New 8T SRAM Circuit with Low Leakage and High Data Stability Idle Mode at 70nm Technology

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