Single event burnout hardening of trench shielded power UMOSFET using High-κ dielectrics

Abstract

This study proposes the High-κ dielectric Trench Shielded power UMOSFET (HK TS-UMOSFET) to be assessed using the two-dimensional numerical simulations. The simulations are employed to evaluate HK TS-UMOSFETs susceptibility to single-event burnout (SEB) mechanism. Based on the findings, the influence of alternative high permittivity gate dielectrics to silicon dioxide (SiO 2 ) in TS-UMOSFET was discussed. Furthermore, in order to improve the performance of the device, its electrical behaviour was simulated with several high-κ dielectrics including Al 2 O 3 , Si 3 N 4 and Aluminium Nitride (AlN). When heavy ions strike the sensitive areas of the device, the electric field distribution and SEB threshold values were extracted. Based on the values yielded, (AlN) was identified as a promising high-κ material to achieve SEB-hardened TS-UMOSFET compared to the other highκ dielectrics. In conclusion, with (AlN), the HK TS-UMOSFET offers a high SEB tolerance and improved electrical characteristics.

A Brief Review of Single-Event Burnout Failure Mechanisms and Design Tolerances of Silicon Carbide Power MOSFETs

“…Some other common power UMOSFET designs include a "buried" P+ layer underneath the gate oxide to act as a shield (see Figure 13b). This additional layer can reduce peak electric fields at this area when under high voltages to enable optimization, but it trades off with on-resistance [81].…”

“…Some other common power UMOSFET designs include a "buried" P+ layer underneath the gate oxide to act as a shield (see Figure 13b). This additional layer can reduce peak electric fields at this area when under high voltages to enable optimization, but it trades off with on-resistance [81]. Experimental studies of Si UMOSFETs show their susceptibility to degradation and catastrophic SEEs under radiation [82][83][84][85][86][87][88][89] and reveal similar performances to VDMOSFETs.…”