Single-Event Effect Responses of Integrated Planar Inductors in 65-nm CMOS

Biereigel, Stefan; Kulis, Szymon; Leroux, Paul; Moreira, P.; Koelpin, Alexander; Prinzie, Jeffrey

doi:10.1109/tns.2021.3121029

Cited by 11 publications

(9 citation statements)

References 27 publications

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“…The responses of the circuit to this effect have been confined to phase excursions below 250 ps. This sensitivity has been previously discussed in [30].…”

Section: Radiation Testingmentioning

confidence: 59%

“…These measurements can be summarized as follows: A large cross-section but low magnitude sensitivity can be attributed to the spiral inductor. Temporary, positive frequency errors of the oscillator are stimulated by the irradiation of this large area [30]. This effect, while responsible for a saturation cross-section on the order of 1 × 10 −3 cm 2 in this circuit, will not be discussed further here, as it exists in LC oscillators using planar inductors regardless of their loop architecture and also only results in small phase errors that scale with LET.…”

Section: Radiation Testingmentioning

confidence: 99%

“…Ions with Linear Energy Transfer (LET) between 3.3 MeV cm 2 mg −1 to 62.5 MeV cm 2 mg −1 were used for the measurement of the circuit cross-section. One of the PLL circuit clock outputs was instrumented with a transient phase measurement system, offering a resolution of 4 ps, as described in [30].…”

Section: Radiation Testingmentioning

confidence: 99%

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Radiation-Tolerant All-Digital PLL/CDR with Varactorless LC DCO in 65 nm CMOS

et al. 2021

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This paper presents the first fully integrated radiation-tolerant All-Digital Phase-Locked Loop (PLL) and Clock and Data Recovery (CDR) circuit for wireline communication applications. Several radiation hardening techniques are proposed to achieve state-of-the-art immunity to Single-Event Effects (SEEs) up to 62.5 MeV cm2 mg−1 as well as tolerance to the Total Ionizing Dose (TID) exceeding 1.5 Grad. The LC Digitally Controlled Oscillator (DCO) is implemented without MOS varactors, avoiding the use of a highly SEE sensitive circuit element. The circuit is designed to operate at reference clock frequencies from 40 MHz to 320 MHz or at data rates from 40 Mbps to 320 Mbps and displays a jitter performance of 520 fs with a power dissipation of only 11 mW and an FOM of −235 dB.

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“…The responses of the circuit to this effect have been confined to phase excursions below 250 ps. This sensitivity has been previously discussed in [30].…”

Section: Radiation Testingmentioning

confidence: 59%

Section: Radiation Testingmentioning

confidence: 99%

See 1 more Smart Citation

Radiation-Tolerant All-Digital PLL/CDR with Varactorless LC DCO in 65 nm CMOS

et al. 2021

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“…Only at the highest LET Si could transients exceeding the random jitter of the PLL be detected [8]. The cross section of the LC ADPLL is much larger in comparison, and the root causes for this sensitivity in the LC DCO have been identified in the used inductor geometry and the switched-capacitor cells used in the PVT and acquisition banks, as discussed in [6,13].…”

Section: Single-event Effects Testingmentioning

confidence: 99%

Radiation-tolerant all-digital clock generators for HEP applications

Biereigel¹,

Kulis²,

Mendes³

et al. 2023

J. Inst.

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The emergence of high-precision timing systems in High Energy Physics motivates new developments in the domain of clock generation and distribution. Particularly, when considering the challenges arising from adopting advanced deep-submicron CMOS technology nodes, all-digital PLL and clock and data recovery (CDR) architectures constitute a promising option for future high energy physics (HEP) experiments. Both LC oscillator and ring oscillator-based all-digital PLL/CDR blocks for front-end ASICs were studied, designed, manufactured and characterized. Their design, the hardening considerations, as well as the performance obtained with these circuits are presented in this article.

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“…With the continuous reduction in the feature size of integrated circuit devices and the rapid development of the aerospace industry, the phase-locked loop (PLL) operated in the radiation environment is seriously affected by the single-event effect, which cannot be ignored [1,2]. When high-energy particles act on the PLL, it will induce the singleevent effect, which will make the frequency and phase of the output signal of the PLL drift and cause the circuit system function to be abnormal [3][4][5]. Each module of the PLL has a different response to the single-event effect [6,7].…”

Section: Introductionmentioning

confidence: 99%

A Single-Event-Hardened Scheme for Ring Oscillator Applied to Radiation-Resistant PLL Microsystems

2023

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A voltage-controlled oscillator (VCO) is one of the key modules of the phase-locked loop (PLL) microsystem, and it is easy to bombard using high-energy particles in a radiation environment, resulting in the single-event effect. In order to improve the anti-radiation ability of the PLL microsystems used in the aerospace environment, a new voltage-controlled oscillator hardened circuit is proposed in this work. The circuit consists of delay cells with an unbiased differential series voltage switch logic structure with a tail current transistor. By reducing sensitive nodes and using the positive feedback of the loop, the recovery process of the VCO circuit to the single-event transient (SET) is reduced and accelerated, so as to reduce the sensitivity of the circuit to the single-event effect. The simulation results based on the SMIC 130 nm complementary metal–oxide–semiconductor (CMOS) process show that the maximum phase shift difference of the PLL with the hardened VCO is reduced by 53.5%, which shows that the hardened VCO structure can reduce the sensitivity of the PLL to the SET and improve the reliability of the PLL in the radiation environment.

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Single-Event Effect Responses of Integrated Planar Inductors in 65-nm CMOS

Cited by 11 publications

References 27 publications

Radiation-Tolerant All-Digital PLL/CDR with Varactorless LC DCO in 65 nm CMOS

Radiation-Tolerant All-Digital PLL/CDR with Varactorless LC DCO in 65 nm CMOS

Radiation-tolerant all-digital clock generators for HEP applications

A Single-Event-Hardened Scheme for Ring Oscillator Applied to Radiation-Resistant PLL Microsystems

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