Single Event Gate Rupture in 130-nm CMOS Transistor Arrays Subjected to X-Ray Irradiation

Abstract

Abstract-We present new experimental results on heavy ion-induced gate rupture on deep submicron CMOS transistor arrays. Through the use of dedicated test structures, composed by a large number of 130-nm MOSFETs connected in parallel, we show the response to heavy ion irradiation under high stress voltages of devices previously irradiated with X-rays. We found only a slight impact on gate rupture critical voltage at a LET of 32 MeV cm 2 mg 1 for devices previously irradiated up to 3 Mrad(SiO 2 ), and practically no change for 100 Mrad(SiO 2 ) irradiation, dose of interest for the future super large hadron collider (SLHC).

Scaling effects of single-event gate rupture in thin oxides

“…It is well known that SEGR can initiate permanent damage in power MOSFETs, MOS capacitors, antifuse devices, etc. [1][2][3][4][5] Meanwhile, simulation methods have been used to help understand the underlying mechanism of single-event effects or predict the vulnerability of specified devices. [6][7][8] These methods can also help to deal with single event gate rupture.…”

“…Researchers from Padova University have introduced a three-dimensional (3D) simulation tool to study the SEGR effect in MOS capacitors. [3,4] Therefore, other researchers have studied the SEGR effect in power MOSFETs using simulation tools. [6][7][8] However, they all focused on the excess holes pileup on the Si-SiO 2 interface and neglected the physical mechanisms within oxides.…”