Single-event-induced charge collection and direct channel conduction in submicron MOSFETs

Abstract

The singleevent (SE) charge collection of an n-channel submicron MOSFET is described using three dimensional device simulations. Ion hits in the drain and in the channel region are considered. For submicron MOSFETs, we show simulation evidence that there may exist a direct source-drain conduction process induced by the ion, called ion-triggered channeling (ITC), which may be an important SE upset mechanism in deep submicron scaling. The further study of of the MOSFET, which is typically the sensitive node. This quantity of charge is used as an indicative measure of a probable failure. Apart from describing this charge collection process, the aim of this study is also to highlight any charge enhancement process unique to submicron FETs. In particular, we have used a 3 4 Bolman transport code to study such a unique process, which we believe may be a dominant factor in the upset vulnerability of deep submicron CMOS. SIMULATION METHODOLOGYIn this work, a three-dimensional carrier transport code, [21 , has been used to model the single event hit at the device level. Using a 3-d simulator provides increased ion-track-length to device-gate-length ratios indicate that the direct source-drain conduction process assumes increased importance for increased scaling.

Basic mechanisms and modeling of single-event upset in digital microelectronics

“…This mechanism was revealed by 3-D alpha-particle simulations and has been experimentally verified. The experiments indicate that source charge injection due to this mechanism increases rapidly for effective gate lengths below about 0.5 m. Later work predicted the same direct channel conduction mechanism can occur in 0.3-m gate length MOSFETs even for normal incidence strikes and can lead to charge multiplication [60]. This mechanism may forebode a serious vulnerability to SEU for deep submicron MOSFETs.…”

Experimental and simulation studies of single-event transient in partially depleted SOI MOSFET *

“…The slow tail is usually caused by carrier diffusion. [17] If body contact can work efficiently, the duration of the tail will be short. Owing to the existence of body contacts, the holes 098505-2 in the device body could be evacuated immediately and the floating body effect is suppressed.…”

SEU reliability analysis of advanced deep-submicron transistors

“…It has also been reported in the literature that source doping plays an important role in charge collection during SEU [11]. Higher source dopings can support larger drift current and would be capable of sourcing more carriers during the barrier lowering, assisting SEBL.…”

“…For channel lengths comparable to the ion track, the radial field sets up a potential gradient that encompasses the entire channel region and removes the barrier at source. The effect was first reported in similar form in [11], where it was named ion-triggered-channeling. However, we quantify it as single-event induced barrier lowering, or SEBL [5], which refers to the ratio of , the change in barrier: before and after the strike (at the midpoint along the channel) and , the absolute barrier before the strike (at the same point of the channel) as seen in Fig.…”