SEU reliability analysis of advanced deep-submicron transistors

Abstract

Abstract-A systematic evaluation of the single-event-upset (SEU) reliability of the advanced technologies-high-gate dielectric, elevated source-drain (E-SD), and lateral asymmetric channel (LAC) MOSFETs is presented for the first time in this work. Our simulations results gives a clear view of how the short channel effects in a device governs its SEU reliability and how this reasoning evolves at the circuit level. It is shown that devices with worsened short-channel effects (high-gate dielectric transistors) have a significantly reduced SEU-reliability in contrast to the devices with controlled short-channel effects (LAC and E-SD) or even a conventional device.Index Terms-charge enhancement, elevated source-drain, high-, lateral asymmetric channel (LAC), single event upset (SEU), short channel effects, scaling, SRAM.

Soft error study in double gated FinFET-based SRAM cells with simultaneous and independent driven gates

“…Single Event Upsets have become an important reliability concern in the development of memories [1]. Soft errors can severely limit the reliability of electronic systems.…”