Soft error study in double gated FinFET-based SRAM cells with simultaneous and independent driven gates

Ramakrishnan, V.; Srinivasan, R.

doi:10.1016/j.mejo.2012.05.014

Cited by 19 publications

(5 citation statements)

References 14 publications

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“…The details of rise time, fall time, pulse width etc. of data and access pulses used in SRAM simulations are given in Table II. Apart from the general device models like doping dependency of mobility, high field saturation and normal electric fields on mobility, for radiation analysis heavy ion impact is activated by in the physics section of SDEVICE [6]. The characteristics of heavy ion like direction, radial distance, LET value and striking location are specified.…”

Section: Simulator and Simulation Methodologymentioning

confidence: 99%

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SEU study of 4T, 6T, 7T, 8T, 10T MOSFET based SRAM using TCAD simulation

Bhuvaneshwari¹,

Sai²,

Kumar³

et al. 2014

International Conference on Information Communication and Embedded Systems (ICICES2014)

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Section: Simulator and Simulation Methodologymentioning

confidence: 99%

“…The amount of critical charge required to flip the memory cell decreases with scaling [4]. Soft error studies of deep submicron MOSFET-based 6T-SRAMs are dealt in detail in [5,6]. In this paper, we have explored the radiation performance of the various SRAM topologies using Sentaurus TCAD simulator.…”

Section: Introductionmentioning

confidence: 99%

SEU study of 4T, 6T, 7T, 8T, 10T MOSFET based SRAM using TCAD simulation

Bhuvaneshwari¹,

Sai²,

Kumar³

et al. 2014

International Conference on Information Communication and Embedded Systems (ICICES2014)

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“…DG-FinFET consist of front gate and back gate.The back gate biasing of the PU, PD and PG leads to ten different topologies [7,8] .They are described as follows The methodology commonly used to study transient effects as SEU couples SPICE simulations with current injection. The current pulse is extracted from other kind of simulations or more often modeled.…”

Section: B Simulation Methodologymentioning

confidence: 99%

Study of Single Event Upsets in different double gate FinFET based SRAM topologies

Srikanth¹,

Vinodhkumar²,

Nagarajan³

et al. 2013

2013 IEEE International Conference ON Emerging Trends in Computing, Communication and Nanotechnology (ICECCN)

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Soft errors also known as Single Event Upsets (SEU) is a term that defines the non-permanent errors caused in microelectronic circuits when high energy particles strike at the sensitive regions of the devices. In this paper, independently driven double gate (IDDG) FinFET and simultaneously driven double gate (SDDG) FinFET based 6T-SRAM cells are studied for their soft error performance. Ten different topologies, nine IDDG based topologies namely Flex-V TH , Flex PG, PG-SN, PG-OSN, Flex PD, Flex PU, Flex-cell, Flex PUPG, Flex PDPG and one SDDG based topology are studied to find out the minimum dose required to flip the value stored in the SRAM cell using TSPICE simulations with 45 nm PTM model. Flex-PG and PG-OSN are having better immunity to radiation and a critical dose value of 1.18 MeV-cm 2 / mg.

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“…In recent studies, the soft-error performance of a 6T SRAM cell has been analyzed with sub-nanometer devices. It was found that the FinFET-based SRAM cell showed better immunity due to soft error in comparison with its conventional counterpart, the CMOS SRAM cell [11][12][13]. Moreover, in the literature, a technique called radiation hardening by design (RHBD) is used to eliminate the effect of SEU during circuit level implementation [14][15][16].…”

Section: Introductionmentioning

confidence: 99%

Soft-Error-Aware Radiation-Hardened Ge-DLTFET-Based SRAM Cell Design

et al. 2023

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In this paper, a soft-error-aware radiation-hardened 6T SRAM cell has been implemented using germanium-based dopingless tunnel FET (Ge DLTFET). In a circuit level simulation, the device-circuit co-design approach is used. Semiconductor devices are very prone to the radiation environment; hence, finding out the solution to the problem became a necessity for the designers. Single event upset (SEU), also known as soft error, is one of the most frequent issues to tackle in semiconductor devices. To mitigate the effect of soft error due to single-event upset, the radiation-hardening-by-design (RHBD) technique has been employed for Ge DLTFET-based SRAM cells. This technique uses RC feedback paths between the two cross-coupled inverters of an SRAM cell. The soft-error sensitivity is estimated for a conventional and RHBD-based SRAM cell design. It is found that the RHBD-based SRAM cell design is more efficient to mitigate the soft-error effect in comparison to the conventional design. The delay and stability parameters, obtained from the N-curve, of the Ge DLTFET-based SRAM cell performs better than the conventional Si TFET-based SRAM cell. There is an improvement of 305x & 850x in the static power noise margin and write trip power values of the Ge DLTFET SRAM cell with respect to the conventional Si TFET SRAM cell.

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Soft error study in double gated FinFET-based SRAM cells with simultaneous and independent driven gates

Cited by 19 publications

References 14 publications

SEU study of 4T, 6T, 7T, 8T, 10T MOSFET based SRAM using TCAD simulation

SEU study of 4T, 6T, 7T, 8T, 10T MOSFET based SRAM using TCAD simulation

Study of Single Event Upsets in different double gate FinFET based SRAM topologies

Soft-Error-Aware Radiation-Hardened Ge-DLTFET-Based SRAM Cell Design

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