Single event multiple upset-tolerant SRAM cell designs for nano-scale CMOS technology

Abstract

Abstract:In this article, two soft error tolerant SRAM cells, the so-called RATF1 and RATF2, are proposed and evaluated. The proposed radiation hardened SRAM cells are capable of fully tolerating single event upsets (SEUs).Moreover, they show a high degree of robustness against single event multiple upsets (SEMUs). Over the previous SRAM cells, RATF1 and RATF2 offer lower area and power overhead. The Hspice simulation results through comparison with some prominent and state-of-the-art soft error tolerant SRAM cells show that our proposed robust SRAM cells have smaller area overhead (RAFT1 offers 58% smaller area than DICE), lower power delay product (RATF1 offers 231.33% and RATF2 offers 74.75% lower PDP compared with DICE), much more soft error robustness, and larger noise margins.

Design of a Radiation Hardened Register File for Highly Reliable Microprocessors

“…The relevant equations are: (5) And: (6) To calculate the error probability of our proposed circuit, it is considerable that our structure can mask 1 and 2-bit errors while the TMR can mask only one error. Therefore, the equation for error probability of a w-bit word is obtained by (7). (7) Fig.5, compares the error probability of the error correcting codes specified by equations 1 to 7 assuming a w of 64.…”

“…Technology shrinking that comes with decrease in supply voltage, affects the sensitivity of the SRAM cells to soft errors [5][6][7][8]. Fig.1 depicts the relation between the technology size, supply voltage and Q crit (the minimum charge needed for a particle strike to result in an SEU).…”

“…The phenomenon of a bit flip in a memory cell such as a flip-flop or latch induced by a particle strike is called single-event upset (SEU). When an energetic particle hits more than one memory cell and causes more than one bit flip, a multi-bit upset (MBU) is happened [6][7][8].…”

A Novel Radiation Hardened Parallel IO Port for Highly Reliable Digital IC Design

“…To mitigate SEUs and SETs in logic circuits, triple modular redundancy (TMR) is a very conventional and widely used techniques in all levels of abstraction [8][9]. Employing three flip-flops with a voter circuit instead of one flip-flop in sequential parts can mask an SEU in one of the flip-flops and result in significant improvement in reliability of the circuit.…”

“…To combat with the aforementioned soft errors, various techniques in all levels of abstraction are suggested [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15]. One costbenefit technique for improving the robustness of digital circuits against soft errors is radiation hardening by design [1,3,[7][8][9][10]. However, along with the more and more decrease in CMOS dimensions, the issue of single event multiple-node upset has been emerged [3,9].…”