Single-Event Transient Pulse Quenching in Advanced CMOS Logic Circuits

Impact of Logic Synthesis on Soft Error Rate of Digital Integrated Circuits

“…This result is consistent with pulse quenching studies such as (Albhin et al, 2009), where the effect of the transient is minimized by charge sharing of closely spaced nodes. For the XOR2 and XNOR2 cells, the pulse width efficiency is higher (Figure 7.3) because the original XOR2 and XNOR2 cells had pulse widths that were higher than any other cells.…”

“…However, this tool has only been used in conjunction with HSPICE to pre-characterize a cell library. This estimation ignores mechanisms that cannot be captured in a SPICE-level model such as pulse quenching (Albhin et al, 2009). Additionally, the cell library used with this tool contained only four cells, which does not account for the trends that could be observed using a broader and more complex range of cells.…”

Single Event Transients and Pulse Quenching Effects in Bandgap Reference Topologies for Space Applications

“…Although Xe ions have a higher LET than Kr ions, the cross-section for Xe-ion-induced ASETs is lower than the cross-section of Kr-ion-induced ASETs. This paradox can be explained through the pulse quenching phenomenon [2], [64]- [66], which has been previously observed or used to mitigate SETs in other analog or digital circuits such as digital inverters, current sources, switched capacitor amplifiers, continuous time amplifiers, folded cascode amplifiers and differential circuits design [6], [23], [63], [67]- [74]. In the next section we justify the measured results by focussing on the key topological difference between the two circuit classes, i.e.…”

“…Paradoxically the σ of the SCM-1.8V drops significantly both in comparison to the CCM-3.3V and in comparison to its Kr σ result, with almost half the LET. This anomaly can only be explained by the pulse quenching phenomenon, that has been observed in other circuits [63].…”

SEU hardened layout design for SRAM cells based on SEU reversal

“…the adjacent device in the back of active device in logic). SEUR is similar to the quenching effect which can quench SET in the logic circuit [11]. The process of SEUR is described as follows: after the active device triggering the first upset, the passive device changes its state to OFF and then collects the deposited charge to trigger the second upset.…”