Single event upset characterization of the Pentium(R) MMX and Celeron(R) microprocessors using proton irradiation

Hiemstra, David M.; Baril, A.

doi:10.1109/redw.2000.896267

Cited by 11 publications

(14 citation statements)

References 8 publications

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“…1 The high energy of ion beams delivered by this facility allows for high penetration depths which are of primary importance for the purposes of this study. Before irradiation, devices were programmed to different levels by controlling the number of electrons stored in the FG.…”

Section: Experimental and Devicesmentioning

confidence: 99%

“…I N SPACE or in other radiation-harsh environments, single high energy ions are known as sources for static or dynamic errors (Single Event Upset, SEU) in many microelectronics circuits, such as complex microprocessors [1], [2] or FPGA [3], [4]. In particular, SEUs are particularly interesting to study in devices often very vulnerable such as memory arrays; also, their repetitive and dense structure makes memory devices relatively easy to model.…”

Section: Introductionmentioning

confidence: 99%

“…Many studies have been conducted regarding all types of memories, with particular emphasis for DRAM [5]- [7] and SRAM [4]- [10]. The device cross section per bit is usually defined as (1) where is the number of bits in the array under study, and is the fluence of a given ion. To obtain a complete cross section vs. LET sensitivity, one needs to repeat the experiment for many different ions, which is often very complex, if not unfeasible at all, because of the cost of beam time and of the actual availability of different ion beams at accelerators.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Angular Dependence of Heavy Ion Effects in Floating Gate Memory Arrays

Cellere

Paccagnella

Visconti

et al. 2007

IEEE Trans. Nucl. Sci.

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Single, high energy, high LET, ions impacting on a Floating gate array on grazing or near-grazing angles lead to the creation of long traces of FGs with corrupted information. Up to 30 consecutive devices can be involved in the trace left by a single ion. We demonstrate that charge collection at multiple nodes can be expected as the technology advances. One of the major implications is that the widely adopted cosine law should be used with great care when dealing with modern devices, with sizes smaller than 100 nm.Index Terms-Floating gate memories, multiple bit upset, single bit upset.

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Section: Experimental and Devicesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Angular Dependence of Heavy Ion Effects in Floating Gate Memory Arrays

Cellere

Paccagnella

Visconti

et al. 2007

IEEE Trans. Nucl. Sci.

View full text Add to dashboard Cite

show abstract

“…The MMX's (rated for 233 MHz operation), tested at 233 MHz and 200 MHz previously [2,3,4], were manufactured on a 0.35 µm gate length CMOS process. It has a transistor count of 4.5 million, operates at 2.8 Vdc and has 16 kbyte of L1 code and data cache on die [14].…”

Section: Proton Irradiationmentioning

confidence: 99%

“…Based on the test results obtained and using the Figure of Merit (FOM) technique [1], the SEU rates for the P4, PIII, and LPMMX, are determined on the Space Shuttle, for the space station orbit. The results are compared with those previously reported for the Pentium MMX (MMX), Pentium II (PII), Celeron, and LPMMX microprocessors [2,3,4]. A comparison of the SEU performance of various Intel x86 processors previously tested is made [5,6].…”

Section: Introductionmentioning

confidence: 99%