Single-event upset in commercial silicon-on-insulator PowerPC microprocessors

Irom,; Farmanesh,; Johnston,

doi:10.1109/soi.2002.1044476

Cited by 23 publications

(37 citation statements)

References 4 publications

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“…The LET of a particle is multiplied by the charge collection depth to obtain the total electron-hole pairs generated by a strike. For process technologies of 180-nm and higher, the charge collection depth does not change significantly and is typically 2 µm in epitaxial (as well as bulk) substrates [16], [22]. This gives an upper bound of 0.3 pC for deposited charge in the 180-nm process technology.…”

Section: A Choosing Worst Case Deposited Chargementioning

confidence: 99%

“…This gives an upper bound of 0.3 pC for deposited charge in the 180-nm process technology. For smaller feature sizes, the charge collection efficiency decreases primarily due to higher channel doping density and a decrease in active layer thickness, which reduces depletion width and channel funneling [16], [17]. In [12], an inverse linear relation between collected charge and doping density was determined empirically.…”

Section: A Choosing Worst Case Deposited Chargementioning

confidence: 99%

“…SOI processes, which can reduce the charge collection depth, were expected to provide a significant increase in SEU immunity. However, research [9], [16] has shown that partially depleted SOI, used to manufacture commercial devices, is comparable to bulk processes in SEU sensitivity, and that scaling of SOI will result in a higher soft error susceptibility just as in bulk processes.…”

Section: Introductionmentioning

confidence: 99%

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Gate sizing to radiation harden combinational logic

Zhou

Mohanram

2006

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

281

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Abstract-A gate-level radiation hardening technique for costeffective reduction of the soft error failure rate in combinational logic circuits is described. The key idea is to exploit the asymmetric logical masking probabilities of gates, hardening gates that have the lowest logical masking probability to achieve costeffective tradeoffs between overhead and soft error failure rate reduction. The asymmetry in the logical masking probabilities at a gate is leveraged by decoupling the physical from the logical (Boolean) aspects of soft error susceptibility of the gate. Gates are hardened to single-event upsets (SEUs) with specified worst case characteristics in increasing order of their logical masking probability, thereby maximizing the reduction in the soft error failure rate for specified overhead costs (area, power, and delay). Gate sizing for radiation hardening uses a novel gate (transistor) sizing technique that is both efficient and accurate. A full set of experimental results for process technologies ranging from 180 to 70 nm demonstrates the cost-effective tradeoffs that can be achieved. On average, the proposed technique has a radiation hardening overhead of 38.3%, 27.1%, and 3.8% in area, power, and delay for worst case SEUs across the four process technologies.

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Section: A Choosing Worst Case Deposited Chargementioning

confidence: 99%

Section: A Choosing Worst Case Deposited Chargementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Gate sizing to radiation harden combinational logic

Zhou

Mohanram

2006

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

281

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“…The design improves the circuit's tolerance to highly-charged particles, reducing the chance of SEU occurrence. Irom et al [7] compare SEU error rates in SoI microprocessors to conventional microprocessors. SEU rates were observably lower in SoI microprocessors.…”

Section: Related Workmentioning

confidence: 99%

A Software Approach to Protecting Embedded System Memory from Single Event Upsets

Zhai

Switzer

et al. 2015

Lecture Notes in Computer Science

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Abstract. Radiation from radioactive environments, such as those encountered during space flight, can cause damage to embedded systems. One of the most common examples is the single event upset (SEU), which occurs when a high-energy ionizing particle passes through an integrated circuit, changing the value of a single bit by releasing its charge. The SEU could cause damage and potentially fatal failures to spacecraft and satellites. In this paper, we present an approach that extends the AVR-GCC compiler to protect the system stack from SEUs through duplication, validation, and recovery. Three applications are used to verify our approach, and the time and space overhead characteristics are evaluated.

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“…With the advent of stereo vision cameras and increased processing power available at lower costs, saliency models that incorporate depth cues have emerged in literature, however, computing depth from disparity is a computationally expensive process [24, 25,26] that planetary rovers can ill afford [27], which makes the algorithm inept at operating in real-time due to limited processing power available on planetary rovers [28,29]. Photoclinometry or shape from shading (SfS) is a cluster of techniques for estimating topography that have been exploited by planetary scientists for more than 50 years [30].…”

mentioning

confidence: 99%