Single Event Upset in SOS Integrated Circuits

The Impact of Delta-Rays on Single-Event Upsets in Highly Scaled SOI SRAMs

“…Like silicon-on-sapphire (SOS) technologies, SOI exhibits a parasitic bipolar structure [11], [12]. An ion strike on an nMOSFET results in the generation and storage of holes within the body of the device, effectively lowering the barrier between the source and body junction of the device, which forward biases the junction until recombination processes eliminate enough of the holes to allow bias conditions to restore device operation [12].…”

Rate prediction for single event effects-a critique

“…The circuit calculation should lead to the critical charge of the median cell if nominal circuit parameters are used. Several examples exist in the literature where a careful calculation has been performed, but when the results are compared with a charge derived from the measured onset threshold, it is necessary to assume an unexpected charge collection depth or an unexpected charge multiplication factor to reconcile the calculations with the experiment [45,46,47,48,49,50]. These authors all discuss their expected charge collection depths based on the technology.…”