Single low‐gain amplifier compensated hybrid delta‐sigma modulator

Abstract

This article presents low-power circuit design techniques to achieve third-order noise shaping by employing multiple stages of passive switched-capacitor gain-boosted integrator and a passive switched-capacitor integrator. First integrator is a passive switched-capacitor for higher linearity. Second integrator is a three-stage passive switched-capacitor gain-boosted integrator to provide passive gain to the loop filter as well as the second DAC feedback. While the third integrator is a two-stage passive switched-capacitor gain-boosted integrator to provide passive gain as well as third DAC feedback for higher stability. Multiple lower stages of passive switched-capacitor gain-boosted integrators employed to enhance the noise shaping order of the modulator and suppress the parasitic effect. The preamplifier is the only active block, while the dynamic comparator used as single-bit quantiser. The complete transistor level with thermal noise simulation can achieve 84 dB of dynamic range (DR), 78.2 dB signal-to-noise-plus-distortion ratio (SNDR), and 78.5 dB signal-to-noise ratio (SNR) for 500 Hz signal bandwidth. It can also achieve signal-to-spurious-free dynamic range (SFDR) of 78.2 dB with estimated power consumption of 220 nW at 1 V supply voltage in SMIC 28 nm CMOS Technology. Finally, it can achieve state-of-the-art Walden Figure-of-Merit (FoM W) of 33 fJ/Conv-Step and Schreier FoM S of 171.2 dB.