Single mask solution to pattern BLP and SNLP using 0.33NA EUV for next-generation DRAM manufacturing

Sah, Kaushik; Cross, Andrew; Das, Sayantan; Fallica, Roberto; Lee, Jeong-Hoon; Kim, Ryan Ryoung; Halder, Sandip; Maguire, Ethan; Armeanu, Ana-Maria; Sears, Monica Kempsell; Lafferty, Neal; Liubich, Vlad; Wei, Chih-I; Fenger, Germain

doi:10.1117/12.2645953

International Conference on Extreme Ultraviolet Lithography 2022 2022

DOI: 10.1117/12.2645953

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Single mask solution to pattern BLP and SNLP using 0.33NA EUV for next-generation DRAM manufacturing

Kaushik Sah¹,

Andrew Cross²,

Sayantan Das³

et al.

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Cited by 3 publications

(1 citation statement)

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“…The honeycomb array hole layer has the highest density among various hole array types, and it is a complex lithography step since this layer is key in determining the performance of the DRAM. BLP with SNLP includes hole type and bi-directional line/space (L/S) design, and industry is considering a single exposure solution, compared to a three-mask solution using ArF immersion [1]. This BLP layer of 10nm DRAM has 2 different types of pattern topologies, hole array and bi-direction line/space: it is a very challenging single exposure level.In this paper, we discuss patterning challenges that come as consequences of industry trends in DRAM cell size reduction [2,3].…”

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confidence: 99%

Application of resolution enhancement techniques at high NA EUV for next generation DRAM patterning

Armeanu

Malankin²,

Lafferty

et al. 2023

DTCO and Computational Patterning II

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Among several critical layers of DRAM (dynamic random-access memory), capacitor holes of honeycomb arrays and bit-line-periphery (BLP) with Storage Node Landing Pad (SNLP) are the most critical layers in terms of patterning difficulty level. The honeycomb array hole layer has the highest density among various hole array types, and it is a complex lithography step since this layer is key in determining the performance of the DRAM. BLP with SNLP includes hole type and bi-directional line/space (L/S) design, and industry is considering a single exposure solution, compared to a three-mask solution using ArF immersion [1]. This BLP layer of 10nm DRAM has 2 different types of pattern topologies, hole array and bi-direction line/space: it is a very challenging single exposure level. In this paper, we discuss patterning challenges that come as consequences of industry trends in DRAM cell size reduction [2,3]. To keep up with this trend and to propose a single mask solution for bit-line-periphery, storage node landing pads and aggressive cell array pitches are considered along with resolution enhancement techniques (RET) for high-NA anamorphic EUV (NA=0.55) lithography. This study uses computational lithography such as source mask optimization (SMO) to find optimal off-axis illumination and optimal placement of sub-resolution assist features (SRAF) on the mask whilst considering the manufacturing rules checks (MRC constraints) for anamorphic EUV masks. In order to achieve that, a screening Design Technology Co-optimization (DTCO) experiment is done. The purpose is to identify cell array pitches in between 24nm and 32nm which satisfy both scaling requirements and patterning fidelity, preferred orientation of layout, and mask biasing scheme for various cell arrays. Lithography metrics like common depth of focus (cDoF), exposure latitude (EL), image contrast, and image log slope (ILS) are used to decide what is optimal way to expose on wafer. For the sake of completeness of the study, mask materials are compared. Indeed, in EUV domain there is interest to use alternative mask absorbers like Ruthenium alloys as an alternative to Tantalum-based absorbers [4,5,6].

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mentioning

confidence: 99%

Application of resolution enhancement techniques at high NA EUV for next generation DRAM patterning

Armeanu

Malankin²,

Lafferty

et al. 2023

DTCO and Computational Patterning II

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Single mask solution to pattern DRAM LILP layer at 42nm pitch using EUV CAR photoresist

Das,

Yang,

Chen

et al. 2024

Optical and EUV Nanolithography XXXVII

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Logic and memory patterning breakthrough using High-NA lithography

Blanco Carballo,

Roy,

Chowrira

et al. 2024

Photomask Technology 2024

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In this paper we will present initial results for logic and memory features imaged with the TWINSCAN EXE:5000 at the ASML-imec high NA lab after successful etch pattern transfer.For logic applications random logic metal designs (consisting of tight pitches and aggressive tip-to-tips) and corresponding via structures have been characterized for A14 and A10 nodes. As well, bidirectional designs enabled by high NA will be described. For memory applications, results from BLP/SNLP layer for D1d and D0a nodes will be presented.

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Single mask solution to pattern BLP and SNLP using 0.33NA EUV for next-generation DRAM manufacturing

Cited by 3 publications

References 4 publications

Application of resolution enhancement techniques at high NA EUV for next generation DRAM patterning

Application of resolution enhancement techniques at high NA EUV for next generation DRAM patterning

Single mask solution to pattern DRAM LILP layer at 42nm pitch using EUV CAR photoresist

Logic and memory patterning breakthrough using High-NA lithography

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