Single-Phase Fault Tolerant Multilevel Inverter Topologies—Comprehensive Review and Novel Comparative Factors

Rehman, Haroon; Tariq, Mohd; Sarwar, Adil; Alhosaini, Waleed; Ma, Hossain; Batiyah, Salem

doi:10.3390/en15249319

Cited by 16 publications

(6 citation statements)

References 95 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…It generally tells the number of levels an inverter circuit can generate post-fault. In this work, fault tolerance factor (FTF) and complete fault tolerance factor (CFTF), metrics proposed in Rehman et al, 16 are used to evaluate fault tolerance of each topology. The FTF can be calculated as…”

Section: Fault Tolerance Analysismentioning

confidence: 99%

“…It generally tells the number of levels an inverter circuit can generate post‐fault. In this work, fault tolerance factor ( FTF ) and complete fault tolerance factor ( CFTF ), metrics proposed in Rehman et al, 16 are used to evaluate fault tolerance of each topology. The FTF can be calculated as

italicFTF goodbreak= \frac{1}{X} \sum_{i = 1}^{N} G_{i},

where X is the total number of switch and capacitor, N is the total number of fault cases, and G i denotes the total number of output voltage levels for i th fault case under post‐fault reconfiguration operation.…”

Section: Comparison Of Puc5 Ft Puc5 Mpuc5 and Ft Mpuc5mentioning

confidence: 99%

“…The extent of switch failure can also vary according to the circuit and its application. Rehman et al 16 describe several single‐phase FT MLI topologies and their constructional features, advantages, and drawbacks. It also reviewed different FT solutions.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Performance evaluation of five‐level packed U‐cell inverter and its fault‐tolerant variants

Rehman,

Fahad,

Sarwar

et al. 2023

Circuit Theory & Apps

Self Cite

View full text Add to dashboard Cite

SummaryIn the power electronics industry, reliability is of utmost importance to manufacturers. Power semiconductor devices are extensively utilized in multilevel inverters (MLIs), which results in increased failure probability. MLI structures have a significant impact on the system's overall reliability. MLIs with a high degree of reliability reduce system maintenance costs and improve efficiency and the life of the entire system. This paper presents a comprehensive evaluation of five‐level packed U‐cell (PUC5) inverter, modified five‐level PUC (MPUC5) inverter, and their fault‐tolerant (FT) variants with respect to reliability, degree of fault tolerance, power loss and efficiency, and cost. A more accurate reliability evaluation method is used in this work in which failure rates of each component of inverter topologies under healthy and post‐fault conditions are calculated. Hence, this method provides more accurate reliability function of an MLI topology as compared to other methods in which failure rates are assumed to be same for all switches. Typhoon HIL‐402 emulator is used to demonstrate the FT capabilities of topologies in hardware‐in‐the‐loop (HIL) environments.

show abstract

Section: Fault Tolerance Analysismentioning

confidence: 99%

italicFTF goodbreak= \frac{1}{X} \sum_{i = 1}^{N} G_{i},

Section: Comparison Of Puc5 Ft Puc5 Mpuc5 and Ft Mpuc5mentioning

confidence: 99%

See 1 more Smart Citation

Performance evaluation of five‐level packed U‐cell inverter and its fault‐tolerant variants

Rehman,

Fahad,

Sarwar

et al. 2023

Circuit Theory & Apps

Self Cite

View full text Add to dashboard Cite

show abstract

“…The majority of faults in MLI are caused by Open Circuit Fault (OCF) and Short Circuit Fault (SCF) in semiconductor switches. The recently presented single phase FT-MLI topologies are reviwed in [20]. The seven level FT-MLI's are presented in [21]- [28].…”

Section: B Literature Reviewmentioning

confidence: 99%

A Seven Level Fault Tolerant Switched Capacitor Boost Inverter With a Single DC Source

Yarlagadda,

Verma,

Tariq

et al. 2023

IEEE Access

Self Cite

View full text Add to dashboard Cite

A Fault-Tolerant Multi-Level Inverter (FT-MLI) is essential to ensure power supply continuity for crucial applications. At the same time, the cost and efficiency of MLI is also important for its successful use in the commercial market. The existing seven level FT-MLI topologies demand more than one input DC source, which increases the cost function. This article proposes a single DC source seven level FT-MLI topology with minimum number of switches (IGBT) to reduce the cost function. The proposed FT-MLI topology generates seven level output voltage with 1.5 times voltage boosting. In case of open or short circuit fault on any single or multi switch, the topology continues to operate with five level output voltage using reserved switches. It consists of eight active switches, two diodes, two capacitors, six thermal fuses, and three reserved switches. In comparison to the existing seven level fault tolerant (open circuit and short circuit fault) topologies, the suggested structure requires minimum number of component count. The efficiency and power losses of the proposed structure are analyzed theoretically. The proposed topology has an efficiency of 96 % at an output power of 600 W under healthy condition and 97% at an output power of 272 W under post fault condition. The level shift pulse width modulation approach is used to generate required triggering pulse for the switch during pre-fault and post-fault. The proposed topology is simulated in the MATLAB/Simulink platform and experimentally verified using dSPACE 1104. The response of the output voltage and current during the transition from pre-fault to post-post fault for each switch fault are presented.

show abstract

“…The medium voltage multilevel converter is mainly used to connect the new energy generation or battery to the grid, which can effectively reduce the switching frequency, du/dt, electromagnetic interference, and output voltage harmonics [3,4]. Multilevel inverters can be divided into single-power type multilevel inverters [5,6] and multi-power type multilevel inverters [7,8] according to the number of power supplies.…”

Section: Introductionmentioning

confidence: 99%

VSG Control for Cascaded Three-Phase Bridge Based Battery Inverter

Qi,

Zheng

2023

WEVJ

View full text Add to dashboard Cite

With the increasing number of new energy sources connected to the grid, the unbalanced output of three-phase grid-connected inverters and the lack of no inertia and damping characteristics in the traditional microgrid control system will seriously affect the stability of voltage, frequency, and power angle for microgrids. This paper proposes a novel cascaded three-phase bridge inverter topology for the battery system used for the electric vehicle. Compared with traditional cascaded H-bridge inverters, the proposed multilevel inverter can achieve self-adaptive balance for three phases. The mathematical model of a cascaded three-phase bridge inverter is established in this paper. Based on the voltage and current equations of a multilevel inverter, a new modulation strategy named carrier phase-shifted-distributed pulse width modulation (CPSD-PWM) was developed, which is more suitable for cascaded three-phase bridge inverters. The harmonic analytic equations of carrier phase-shifted pulse width modulation (CPS-PWM) and CPSD-PWM are constructed by the double Fourier analysis method. Compared with the traditional PWM modulation strategy, the CPSD-PWM can reduce the output harmonics and improve the balance of the three-phase output, which can realize the three-phase adaptive balance in the cascaded three-phase bridge inverter. This paper develops a cascaded three-phase bridge multilevel power converter system based on the virtual synchronous generator (VSG) control strategy. The voltage and frequency of inverter output can be accurately controlled in both island mode and grid-connected mode through active power-frequency regulation and reactive power–voltage regulation, and the stability of primary frequency regulation for the multilevel microgrid inverter can be improved by collaborative optimization of virtual inertia and virtual damping. The CPSD-PWM modulation strategy and VSG control strategy are verified by the simulation results and experimental data for the cascaded three-phase bridge inverter.

show abstract

Single-Phase Fault Tolerant Multilevel Inverter Topologies—Comprehensive Review and Novel Comparative Factors

Cited by 16 publications

References 95 publications

Performance evaluation of five‐level packed U‐cell inverter and its fault‐tolerant variants

Performance evaluation of five‐level packed U‐cell inverter and its fault‐tolerant variants

A Seven Level Fault Tolerant Switched Capacitor Boost Inverter With a Single DC Source

VSG Control for Cascaded Three-Phase Bridge Based Battery Inverter

Contact Info

Product

Resources

About