Single Shot Logic Patterns: Increasing Diagnostic Resolution of Logic Failures Utilizing Single Fault Targeting and Constraints

Abstract

ATPG diagnosis is an essential part in failure analysis and is proven to be an effective technique in isolating faults in the digital core. In many single failure cases however, ATPG diagnosis could yield either incorrect candidates or includes a large amount of equivalency which limits diagnostic resolution. While iterative ATPG diagnosis improves diagnostic resolution, there are many cases where the resolution is still insufficient. This paper will discuss a methodology that helps the analyst understand and complement ATPG diagnosis by using an approach called “single shot logic patterns”. New patterns that each target one singular fault in the area of interest provide the failure analyst with simplified analytical data. This process is repeated for each suspect candidate. The number of times a target fault is detected is increased for better resolution. Aggregating this analytical data with the layout and fan out of the net instances could provide greater resolution into the likely defective area. Furthermore, adding constraints can also be used to further simplify the test and/or control the fan out of failures. Only equivalencies where there is observable fan out can achieve greater diagnostic resolution. ATPG tools have been observed to not always maximize this fan out.

Maximizing ATPG Diagnosis Resolution on Unique Single Failing Devices

“…SSL can be used after initial and iterative ATPG diagnoses to test the different fault candidates and further isolate the fault in the process. For a more detailed description of SSL patterns, there are previous two papers that introduced SSL and showed examples of how it can be used for logic failures and IDDQ failure [11][12].…”