The failure analysis community working on highly integrated mixed signal circuitry is entering an era where simultaneously System-On-Chip technologies, denser metallization schemes, on-chip dissipation techniques and intelligent packages are being introduced. These innovations bring a great deal of defect accessibility challenges to the failure analyst. To contend in this era while aiming for higher efficiency and effectiveness, the failure analysis environment must undergo a disruptive evolution. The success or failure of an analysis will be determined by the careful selection of tools, data and techniques in the applied analysis flow. A comprehensive approach is required where hardware, software, data analysis, traditional FA techniques and expertise are complementary combined [1]. This document demonstrates this through the incorporation of advanced scan diagnosis methods in the overall analysis flow for digital functionality failures and supporting the enhanced failure analysis methodology. For the testing and diagnosis of the presented cases, compact but powerful scan test FA Lab hardware with its diagnosis software was used [2]. It can therefore easily be combined with the traditional FA techniques to provide stimulus for dynamic fault localizations [3]. The system combines scan chain information, failure data and layout information into one viewing environment which provides real analysis power for the failure analyst. Comprehensive data analysis is performed to identify failing cells/nets, provide a better overview of the failure and the interactions to isolate the fault further to a smaller area, or to analyze subtle behavior patterns to find and rationalize possible faults that are otherwise not detected. Three sample cases will be discussed in this document to demonstrate specific strengths and advantages of this enhanced FA methodology.

ATPG diagnosis is an essential part in failure analysis and is proven to be an effective technique in isolating faults in the digital core. In many single failure cases however, ATPG diagnosis could yield either incorrect candidates or includes a large amount of equivalency which limits diagnostic resolution. While iterative ATPG diagnosis improves diagnostic resolution, there are many cases where the resolution is still insufficient. This paper will discuss a methodology that helps the analyst understand and complement ATPG diagnosis by using an approach called “single shot logic patterns”. New patterns that each target one singular fault in the area of interest provide the failure analyst with simplified analytical data. This process is repeated for each suspect candidate. The number of times a target fault is detected is increased for better resolution. Aggregating this analytical data with the layout and fan out of the net instances could provide greater resolution into the likely defective area. Furthermore, adding constraints can also be used to further simplify the test and/or control the fan out of failures. Only equivalencies where there is observable fan out can achieve greater diagnostic resolution. ATPG tools have been observed to not always maximize this fan out.

In this paper the authors will discuss an application of Single Shot Logic (SSL) patterns used for further localizing IDDQ failures using ATPG constraints and targeted faults. This new method provides the analyst a possibility of performing circuit analysis using IDDQ measurement results as a pass/fail criterion rather than logic mismatches. Once a defective area was partially isolated through fault localization, SSL patterns were created to control individual internal node logic states in a deterministic way. IDDQ was measured at each SSL iteration where schematic analysis can further isolate the failure to a specific location. Two case studies will be discussed to show how this technique was used on actual failing units, with detailed explanation of the steps performed that led to a more precise determination of the fault location in the suspect cell.

This paper will present a practical implementation of ATPG testing and diagnosis in Failure Analysis resulting in a fast and efficient iterative ATPG diagnosis and fault isolation. On this implementation, a compact test HW instead of an ATE is used for cost-effective ATPG testing and characterization capability. The advantages of this implementation are combined with ATPG tools to make it possible to achieve a faster and more efficient implementation of iterative ATPG diagnosis, Dynamic Analysis by Laser Stimulation (DALS) analysis or similar techniques. The requirements needed in order to implement ATPG testing and diagnosis in FA lab will be discussed. Success in determining root cause, especially on the complex analysis cases is determined by the complimentary combination of various fault isolation techniques. Knowledge of the fundamentals of these techniques combined with creative thinking process of the analyst leads to the approaches and solutions that maximize the combined advantages of these techniques.

The advent of lock-in thermal imaging application on semiconductor failure analysis added capability to localize failures through thermal activity (emission) of the die. When coupled with creative electrical set-up and material preparations, lock-in thermography (LIT) [1, 2] application gives more possibility in exploring the failure of the device using low power settings. This gives higher probability of preserving the defect which leads to a more conclusive root cause determination.