SiO₂ Free HfO₂ Gate Dielectrics by Physical Vapor Deposition

Abstract

HfO 2 layers, 25-Å thick, were grown by cyclic Hf sputter deposition and room temperature oxidation steps on chemically oxidized Si(001). Subsequent in situ annealing and TiN deposition yield a high-κ gate-stack for which the original 8-Å-thick SiO 2 layer is eliminated, as confirmed by transmission electron microscopy. Transistors fabricated with this gate-stack achieve an equivalent oxide thickness in inversion T inv = 9.7 Å, with a gate leakage J g = 0.8 A/cm 2 . Devices fabricated without in situ annealing of the HfO 2 layer yield a T inv which increases from 10.8 to 11.2 Å as the oxidation time during each HfO 2 growth cycle increases from 10 to 120 s, also causing a decrease in J g from 0.95 to 0.60 A/cm 2 , and an increase in the transistor threshold voltage from 272 to 294 mV. The annealing step reduces T inv by 1.5 Å (10%) but also increases the gate leakage by 0.1 A/cm 2 (30%), and causes a 61 mV reduction in V t . These effects are primarily attributed to the oxygen-deficiency of the as-deposited HfO 2 , which facilitates both the reduction of an interfacial SiO 2 layer and a partial phase transition to a high-κ cubic or tetragonal HfO 2 phase.Index Terms-HfO 2 , high-k dielectrics, interface scavenging, MOSFET, physical vapor deposition (PVD), SiO 2 interlayer.

An Investigation into the $HfO_2/Si$ Interface: Materials Science Challenges and their Effects on MOSFET Device Performance

“…[4] [7] [16] Jamison et al, reported a process flow consisting of a P V D step followed by a RT A annealing at 750 o C, which showed promise in eliminating the interlayer completely with careful control of the anneal times and oxygen flow concentration, as shown in Figure 9. [31] P V D and annealing in presence of O 2 may prove useful as described in the next section. [31] However, it must be noted that due to incomplete data, no conclusion can be drawn on the mechanism at work.…”

“…[31] P V D and annealing in presence of O 2 may prove useful as described in the next section. [31] However, it must be noted that due to incomplete data, no conclusion can be drawn on the mechanism at work. [8] A safe bet for the mechanism of formation at the interlayer is that, most substrates are not free of native oxide.…”

“…Shin et al, also studies the effects of the local oxygen partial pressure (p o ) on the stability of the phases, when the molar ratio of hafnium to silicon at the interface is set to 1. [9] [10] It can clearly be seen Figure 9: Hf O 2 films directly deposited on a (110) substrate using P V D subjected to an oxidation time of (a) 120 s [31] (b) 10 s [31] (c) 120 s but with an additional anneal step at 750 o C for 5 min [31] (e) Leakage characteristics and gate capacitance of the films. [31] (f ) Threshold voltage as a function of the oxidation time.…”

Heterodielectric oxide‐engineered single‐lateral pocket‐based gated source TFET

“…It is also evident that a high‐field‐induced vertical onset is exhibited at mole fraction of 0.45. Therefore, to assess the HD‐GSLP TFET for symmetrical voltage operations between 1.0 V ≤ V DD ≤ 0.5 V, a physical gate oxide of 2.5 nm ( ε = 22) is assumed keeping in consideration the physically demonstrated ultra‐thin EOTs as low as 0.3 nm 31 and particularly the successful physical demonstration of HfO 2 thin films of 2.5 nm through processes like cyclic physical vapor Hf deposition (PVD) 32 or atomic layer deposition (ALD) followed by rapid thermal crystallization 33 . Moreover, gate tunnel leakage current usually dominates for physical oxide thicknesses lesser than 2 nm 34 .…”

Characterization of the electronic structure and thermal stability of HfO2/SiO2/Si gate dielectric stack

“…HfO 2 has received considerable attention because it possesses excellent scalability along with a big dielectric permittivity (κ) value (>20), a relatively large band gap of 5.8 eV, and compatibility with the conventional transistor process . Industries are converging to integrate the HfO 2 ‐based high‐k gate dielectrics in advanced transistor applications . However, one of the major concerns for application of the HfO 2 dielectrics gate stack in the device is its reliability.…”