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HfO 2 layers, 25-Å thick, were grown by cyclic Hf sputter deposition and room temperature oxidation steps on chemically oxidized Si(001). Subsequent in situ annealing and TiN deposition yield a high-κ gate-stack for which the original 8-Å-thick SiO 2 layer is eliminated, as confirmed by transmission electron microscopy. Transistors fabricated with this gate-stack achieve an equivalent oxide thickness in inversion T inv = 9.7 Å, with a gate leakage J g = 0.8 A/cm 2 . Devices fabricated without in situ annealing of the HfO 2 layer yield a T inv which increases from 10.8 to 11.2 Å as the oxidation time during each HfO 2 growth cycle increases from 10 to 120 s, also causing a decrease in J g from 0.95 to 0.60 A/cm 2 , and an increase in the transistor threshold voltage from 272 to 294 mV. The annealing step reduces T inv by 1.5 Å (10%) but also increases the gate leakage by 0.1 A/cm 2 (30%), and causes a 61 mV reduction in V t . These effects are primarily attributed to the oxygen-deficiency of the as-deposited HfO 2 , which facilitates both the reduction of an interfacial SiO 2 layer and a partial phase transition to a high-κ cubic or tetragonal HfO 2 phase.Index Terms-HfO 2 , high-k dielectrics, interface scavenging, MOSFET, physical vapor deposition (PVD), SiO 2 interlayer.

La x Lu 1 − x O 3 thin films were deposited on 300 mm silicon wafers by physical vapor deposition and fabricated into field-effect transistors using a gate-first process flow. The films were characterized using transmission electron microscopy, Rutherford backscattering spectrometry, and synchrotron x-ray diffraction. The results show the films remain amorphous even at temperatures of 1000 °C. The dielectric properties of LaxLu1−xO3 (0.125≤x≤0.875) thin films were evaluated as a function of film composition. The amorphous LaxLu1−xO3 thin films have a dielectric constant (K) of 23 across the composition range. The inversion thickness (Tinv) of the LaxLu1−xO3 thin films was scaled to <1.0 nm.

Low-temperature epitaxial Si, SiGe, and SiC films were grown in a 300mm cold-wall UHV/CVD reactor on (100) silicon wafers (bulk and SOI) at temperatures ranging from 300 to 800 °C using disilane, germane and methylsilane. Four key advantages of UHV/CVD over RPCVD are demonstrated: (i) higher structural quality of epitaxial Si using disilane as a precursor, (ii) highly controlled growth of ultra-thin Si down to ~ 6 Å, (iii) planar growth of SiGe at ultra low temperature (< 375 ºC), and (iv) planar growth of germanium at temperatures of less than 350 ºC.

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