SiOC CMP developed and implemented in 7nm and beyond

Huang, Haigou; Chao, Taifong; Han, Ja-Hyung; Koli, Dinesh; Fang, Qiang

doi:10.1109/cstic.2017.7919826

Cited by 1 publication

(1 citation statement)

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“…In a new concept, polysilicon is deposited into pillars and remains only in a certain amount before oxide deposition. Since it can be pulled out in a gentle way, the bottom Epi structure remains intact while the polysilicon material and the device performance are not impacted (5)(6). Without poly-Si CMP, the silicon film is not uniform which will cause further variation in the downstream process steps, thus impacting final device performance.…”

Section: Introductionmentioning

confidence: 99%

The Role of Polysilicon Slurry and Its Application in 7nm CMP

et al. 2017

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Polysilicon CMP (Chemical Mechanical Polishing) is a highly critical process for better controlling gate heights, at both wafer level and within-die level, with improved uniformity. Uniform gate height not only determines the transistor performance but also impacts the downstream processes. Many slurry factors play a role in maintaining the gate height uniformity for CMP, namely -type of abrasives, constituents in the slurry, pH of the slurry, etc. In this study, a comparison between ceria-and silica-based slurries was conducted based on their on-wafer performances. The study showed that ceria-based poly slurry resulted in a < 2 nm Within-Die Non-Uniformity (WIDNU) in gate height. Also, this slurry showed a detectable end-point signal and the capability to stop on nitride. However, the dishing in the frame area was > 100 nm. In contrast, the silica-based slurry had better selectivity, removal rate, and dishing performance in the frame and in the pad area. During the experiments it was observed that 92 % reduction in dishing and 270 % improvement in selectivity can be achieved by using the silica-based slurry.

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Section: Introductionmentioning

confidence: 99%