Chemical Mechanical Polishing (CMP) has been used in the manufacturing process for copper (Cu) damascene process. It is well known that dishing and erosion occur during CMP process, and they strongly depend on metal density and line width. The inherent thickness and topography variations become an increasing concern for today's designs running through advanced process nodes (sub 65nm). Excessive thickness and topography variations can have major impacts on chip yield and performance; as such they need to be accounted for during the design stage.In this paper, we will demonstrate an accurate physics based CMP model and its application for CMP-related hotspot detection. Model based checking capability is most useful to identify highly environment sensitive layouts that are prone to early process window limitation and hence failure. Model based checking as opposed to rule based checking can identify more accurately the weak points in a design and enable designers to provide improved layout for the areas with highest leverage for manufacturability improvement. Further, CMP modeling has the ability to provide information on interlevel effects such as copper puddling from underlying topography that cannot be captured in Design-forManufacturing (DfM) recommended rules.The model has been calibrated against the silicon produced with the 45nm process from Common Platform (IBMChartered-Samsung) technology. It is one of the earliest 45nm CMP models available today. We will show that the CMP-related hotspots can often occur around the spaces between analog macros and digital blocks in the SoC designs. With the help of the CMP model-based prediction, the design, the dummy fill or the placement of the blocks can be modified to improve planarity and eliminate CMP-related hotspots. The CMP model can be used to pass design recommendations to designers to improve chip yield and performance.

In advanced node semiconductor manufacturing, Chemical Mechanical Polish (CMP) is a critical process step in formation of many modules, from fin formation, replacement metal gate (RMG), Self-Aligned Contact (SAC), to interconnect. In each application, CMP's stop-on capability is increasingly seen as an essential element in gauging device integrity, and thus is critical to the successful implementation of a technology. This presentation discusses the critical importance of CMP selectivity, how selectivity is measured and modulated, and how the need of stopon capability is balanced with the need to make sure complete residue clearing.

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The CMP challenges for advanced technology nodes are discussed. Global and local uniformity challenges and their cumulative effects are presented. Uniformity improvements for advanced node integration were achieved through slurry, pad and platen optimization, innovative integration schemes, the reduction of incoming variation and the reduction of cumulative effects. We discuss reduction of typical CMP defect types. Defects resulting from simple mechanisms (foreign material, polish residues) and those resulting from chemical and physical interactions (corrosion, chemical attack, scratches, physical migration) and strategies for control are studied. Defectivity reduction measures include new post-CMP clean chemicals, new slurries and pads and reduction of incoming defectivity. Finally we discuss an observed tradeoff between good defectivity and good uniformity.

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