SiP fabricated by W-CSP using excimer laser via-hole formation and Cu electroplating

Abstract

Recently high density packaging technologies have been strongly requested to realize ubiquitous networking society. A wafer-level chip size packaging (W-CSP) technology is one of the most promising technologies for high density and environmental friendly packaging. Purpose of this study is to fabricate system in package (SiP) by using W-CSP technology. In this study, we have fabricated two chip module by W-CSP using excimer laser to form via-holes and electro-plating to fill via-holes. This study has two main new technologies, one is new via-hole formation by using excimer laser that makes small (30m diameter) and deep (50 and 100m) via-holes, a micro-lens array has been used to shorten via-hole formation time. The micro-lens array makes one-line via-hole formation at once. And the other is new copper electroplating techniques to fill via-holes which have same diameter (30m) and different depth (50 and 100m) by controlling additives and agitating conditions. In this study, we have fabricated two chip module, first step, second chip mounting on first chip. The second chips whose thickness was 50 m was mounted on wafer (first chip) that has been finished up wafer process. The second chips have been thinned and mounted by DAF tape. Next, polyimide or epoxy resin whose thickness was about 100 m was coated by spin-coater to cover the mounted chips. Two types of viahole whose depths were different, 50 and 100 m, should be formed by excimer laser to connect pads between the wafer pad and mounted chip pad. The excimer laser have formed two types of via whose diameter was about 30 m. Damage by excimer laser irradiation have been examined by irradiation of laser to gate of FET transistor directly. Properties of FET transistor did not change even after 500 pluses of 400 mJ/cm 2 which are much enough for via-hole formation. To shorten via-hole formation time, a micro-lens array was designed. An ashing process with CF 4 gas has performed to clean surface and inside of via-holes. After viahole formation, seed-layers, sputtered Ti and Cu films are necessary for following copper electro-deposition. By microscopy measurement, the seed-layers were uniformly formed from top to bottom of via-hole. In general mixture of additives, these are brightener, leveler and suppressor, made via-hole filling completely. By controlling leveler effect, the via-hole with 30 m diameter and 100 m depth have been perfectly filled by copper electroplating. Both mechanical agitation and current density is effective to via-hole filling.Moreover, additional electroless copper seed-layer to increase conductivity at near the bottom of via-hole is also effective to suppress voids at the bottom of vai-holes. Therefore, the multi-chip module would be performed by the W-CSP with excimer laser and copper electro-plating.

3-D Integration and Through-Silicon Vias in MEMS and Microsensors

“…In recent years, nano-and femto-second lasers have been widely used for creation of vias on silicon and glass substrates during TSV fabrication [39]- [47]. Laser ablation exploits the high energy density of highly directional lasers to instantly melt the substrates by heating them to the temperatures higher than the melting point, and expel the molten portions by impulse waves.…”

“…2(c), laser drilling rates will decrease with increases in the via diameter and depth [47]. Recently a parallel method has been proposed, using a microlens array to split the laser into multiple beams [39]. However, the maximum number of parallel beams is limited by the power of the laser and the minimum energy [45] (Reprint with permission), (b) Appearance after wet etching/polishing [45] (Reprint with permission), (c) Dependence of etching rates on via diameters and depths [47] (XsiL, reprint with permission from IMAPS).…”