A multi-chip module (MCM) was fabricated using an excimer laser driller and electro-plating. This method contributes to the interconnection properties of the MCM. First, a second chip with a thickness of 50 μm was mounted on a wafer that had been created by a wafer process, and polyimide with a thickness of about 100 μm was applied by a spin-coater to cover the mounted chips. Two types of via-holes, with depths of 50 and 100 μm, were formed by the excimer laser to connect the wafer and mounted chip pads. The excimer laser driller with a micro-lens array formed two types of via with diameters of about 30 μm simultaneously. Damage caused by the excimer laser irradiation was examined by direct laser irradiation of the FET transistor gate. Properties of the FET transistor did not change even after 500 pulses of 400 mJ/ cm 2 which is sufficient for via-hole formation. A micro-lens array was designed to shorten the via-hole formation time.After via-hole formation, a seed-layer of sputtered Ti and Cu films were necessary, followed by copper electro-deposition.Microscopy measurements confirmed that the seed-layers were uniformly formed from top to bottom of the via-hole. Generally the mixture of additives to complete the via-hole filling consists of brightener, leveler, and a suppressor. By controlling the leveler concentration, a via-hole with a diameter of 30 μm and a depth of 100 μm was perfectly filled by copper electroplating. In this way the multi-chip module was created by wafer-level chip size technologies (W-CSP) using an excimer laser driller.

Recently high density packaging technologies have been strongly requested to realize ubiquitous networking society. A wafer-level chip size packaging (W-CSP) technology is one of the most promising technologies for high density and environmental friendly packaging. Purpose of this study is to fabricate system in package (SiP) by using W-CSP technology. In this study, we have fabricated two chip module by W-CSP using excimer laser to form via-holes and electro-plating to fill via-holes. This study has two main new technologies, one is new via-hole formation by using excimer laser that makes small (30m diameter) and deep (50 and 100m) via-holes, a micro-lens array has been used to shorten via-hole formation time. The micro-lens array makes one-line via-hole formation at once. And the other is new copper electroplating techniques to fill via-holes which have same diameter (30m) and different depth (50 and 100m) by controlling additives and agitating conditions. In this study, we have fabricated two chip module, first step, second chip mounting on first chip. The second chips whose thickness was 50 m was mounted on wafer (first chip) that has been finished up wafer process. The second chips have been thinned and mounted by DAF tape. Next, polyimide or epoxy resin whose thickness was about 100 m was coated by spin-coater to cover the mounted chips. Two types of viahole whose depths were different, 50 and 100 m, should be formed by excimer laser to connect pads between the wafer pad and mounted chip pad. The excimer laser have formed two types of via whose diameter was about 30 m. Damage by excimer laser irradiation have been examined by irradiation of laser to gate of FET transistor directly. Properties of FET transistor did not change even after 500 pluses of 400 mJ/cm 2 which are much enough for via-hole formation. To shorten via-hole formation time, a micro-lens array was designed. An ashing process with CF 4 gas has performed to clean surface and inside of via-holes. After viahole formation, seed-layers, sputtered Ti and Cu films are necessary for following copper electro-deposition. By microscopy measurement, the seed-layers were uniformly formed from top to bottom of via-hole. In general mixture of additives, these are brightener, leveler and suppressor, made via-hole filling completely. By controlling leveler effect, the via-hole with 30 m diameter and 100 m depth have been perfectly filled by copper electroplating. Both mechanical agitation and current density is effective to via-hole filling.Moreover, additional electroless copper seed-layer to increase conductivity at near the bottom of via-hole is also effective to suppress voids at the bottom of vai-holes. Therefore, the multi-chip module would be performed by the W-CSP with excimer laser and copper electro-plating.

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Our previous studies showed that co-deposition of refractory metal improves the properties of NiP films, so in this study we examined electroless Ni-W-P and Ni-MoP alloy films as alternatives to Pd films. High heat-resistance is necessary in the intermediate layer of printed wiring boards. The ternary Ni alloy films exhibit high heat-resistance properties. These new intermediate layers were evaluated from the viewpoint of wire-bonding strength. Results indicate that the new intermediate layers have almost the same properties as Pd intermediate layers and lamination. The experimental results also show that the ternary Ni alloy films suppress local corrosion, and Ni diffuses to the Au surface in the same way as a Pd intermediate layer.

In the basic electroforming process, nickel sulfamate plating is extensively applied for the preparation of micro-electro-mechanical systems (MEMS) devices. For this application, nickel films are required for their low internal stress and high hardness. We investigated the influence of bath composition and plating conditions on the mechanical properties of deposited films in the presence of sodium saccharin and 2-butyne-1Ј4-diol as a brightener. Among the several influential variables, the concentration of nickel sulfamate had the greatest influence on physical properties such as hardness and tensile strength of the plating films. The hardness and tensile strength were improved by decreasing the concentration of nickel sulfamate. Consequently, pure nickel films having a hardness of 459 Hv and a tensile strength of 1,306 MPa were obtained from a bath formulated with 50.0 g/dm 3 of nickel sulfamate without brighter. Moreover, we successfully made good cantilever properties using a low-concentration nickel sulfamate bath.