Sleep transistor sizing using timing criticality and temporal currents

Ramalingam, Anand; Zhang, Bin; Devgan, Anirudh; Pan, David Z.

doi:10.1145/1120725.1120832

Cited by 42 publications

(22 citation statements)

References 6 publications

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“…In the pre-processing phase, we compute these values, and then we extract the timing information (path delays) of the design which form the timing constraints. To overcome the problems of path based optimization as discussed in [11], we use the heuristic as described in [11] to extract the timing information of the design. We use a standard static timing analysis engine (PrimeTime c by Synopsys) to extract the longest timing path through each cell in the design.…”

Section: Pre-processingmentioning

confidence: 99%

Physically clustered forward body biasing for variability compensation in nanometer CMOS design

Sathanur

Pullini

Benini

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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Nanometer CMOS scaling has resulted in greatly increased circuit variability, with extremely adverse consequences on design predictability and yield. A number of recent works have focused on adaptive post-fabrication tuning approaches to mitigate this problem. Adaptive Body Bias (ABB) is one of the most successful tuning "knobs" in use today in high-performance custom design. Through forward body bias (FBB), the threshold voltage of the CMOS devices can be reduced after fabrication to bring the slow dies back to within the range of acceptable specs. FBB is usually applied with a very coarse core-level granularity at the price of a significantly increased leakage power. In this paper, we propose a novel, physically clustered FBB scheme on row-based standardcell layout style that enables selective forward body biasing of only of the rows that contain most timing critical gates, thereby reducing leakage power overhead. We propose exact and heuristic algorithms to partition the design and allocate optimal body bias voltages to achieve minimum leakage power overhead. This style is fully compatible with state-of-the-art commercial physical design flows and imposes minimal area blowup. Benchmark results show large leakage power savings with a maximum savings of 30% in case of 5% compensation and 47.6% in case of 10% compensation with respect to block-level FBB and minimal implementation area overhead .

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Section: Pre-processingmentioning

confidence: 99%

Physically clustered forward body biasing for variability compensation in nanometer CMOS design

Sathanur

Pullini

Benini

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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“…The sizing technique, which is straight-forward and follows standard sleep transistor sizing techniques, is omitted. Interested readers may refer to [6] [7] for sleep transistor sizing.…”

Section: Active Mode Performance: Sizing Msmentioning

confidence: 99%

Design and application of multimodal power gating structures

Pakbaznia

Pedram

2009

2009 10th International Symposium on Quality of Electronic Design

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-Designing a power-gating structure with high performance in the active mode and low leakage and short wakeup time during standby mode is an important and challenging task. This paper presents a tri-modal switch cell that enables implementation of multimodal power gating, including active, data-retentive drowsy, and deep sleep modes. A circuit realization and design methodology are presented that allow one to take advantage of the ultra low leakage deep sleep mode, low leakage, but very fast wakeup, drowsy mode, and an additional low leakage data-retentive mode. Experimental results demonstrate the benefits of this new switch and corresponding power gating technique.

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“…Different circuit size granularities have been explored for power gating, although primarily coarse-grain techniques have been applied in industry. Many works have examined issues surrounding power switch sizing, and implemented schemes to accurately assess how much area is required for a given circuit block [11][12][13], by taking into account input patterns and timing criticality of the cells being power gated. In the context of VI, we explore the tradeoffs between circuit size granularities for power gating.…”

Section: B Power Gatingmentioning

confidence: 99%

Place and route considerations for voltage interpolated designs

Brownell

Khan

Brooks

et al. 2009

2009 10th International Symposium on Quality of Electronic Design

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Abstract-Voltage interpolation is a promising post fabrication technique for combating the effects of process variations. The benefits of voltage interpolation are well understood. Its implementation in a VLSI-CAD flow has been considered through the synthesis stage. In this paper we study the implications of place and route on voltage interpolation. We evaluate multiple placement strategies, and conclude that a hybridization of forced placement and cluster boxing techniques results in minimum overhead.

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Sleep transistor sizing using timing criticality and temporal currents

Cited by 42 publications

References 6 publications

Physically clustered forward body biasing for variability compensation in nanometer CMOS design

Physically clustered forward body biasing for variability compensation in nanometer CMOS design

Design and application of multimodal power gating structures

Place and route considerations for voltage interpolated designs

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