Slicing Floorplans with Handling Symmetry and General Placement Constraints

Abstract

Floorplan design is an essential step in physical design of VLSI circuits and its results directly determine the performance of the final packing. Existing floorplanners that use slicing floorplans are efficient in runtime and capable of getting a tight and regular packing, which can significantly improve the routability of placement result. Nevertheless, in order to obtain satisfactory floorplans for analog or mixed-signal circuits, a series of constraints should be considered during this stage, including symmetry, and other general constraints. And, most of these constraints have only been achieved by using nonslicing floorplanners in the present. In this paper, we will present a unified method based on polish expression representation to handle these constraints in slicing floorplans. Experimental results demonstrate that our approach is effective and feasible in solving the constraint-driven slicing floorplan problems.